Abstract: Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain.

Abstract: Provided is a timing controller. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.

Abstract: Provided is a data transmission method, including: sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform clock calibration; sending first configuration information to the source driver chip over a data channel in response to completing the clock calibration by the source driver chip, wherein the first configuration information instructs the source driver chip to perform a configuration on a physical layer parameter; and successively sending a link stable pattern and display data to the source driver chip.

Abstract: The voltage regulator comprises: a voltage regulation circuit, a detection circuit and at least one current source unit. An output terminal of the voltage regulation circuit is electrically connected to a first terminal of each of the current source units, and is configured to be electrically connected to a load; and a second terminal of each of the current source units is electrically connected to a first voltage terminal. The detection circuit is electrically connected to the voltage regulation circuit, and is configured to: when the voltage regulation circuit is in a light-load state, control a designed number of the current source units to connect to the output terminal of the voltage regulation circuit to output designed current, and when the voltage regulation circuit is in a heavy-load state, control each of the current source units to disconnect from the output terminal of the voltage regulation circuit.

Abstract: Embodiments of the disclosure provide a level shift circuit, a chip and a display device. By setting first and second voltage clamping modules, and by adjusting first clamping voltage by controlling bias voltage input to the first voltage clamping module and adjusting second clamping voltage by controlling bias voltage and second bias voltage input to the second voltage clamping module, respective operating and output voltages of the first and the second voltage clamping modules and the shift module are within small range. Therefore, even the level shift circuit is designed by using devices with breakdown voltage lower than the difference between the first and second power supply voltages, the devices in the level shift circuit may be avoid being breakdown. Accordingly, some process platforms that cannot produce high-breakdown voltage devices may produce chips including the level shift circuit in the embodiment, and the restrictions on the process platform are reduced.

Abstract: The present disclosure provides a receiver circuit and a receiver circuit control method. In the present disclosure, the input data is detected by a detection circuit to obtain a data rate detection result, and the bandwidth of the receiver is automatically adjusted according to the data rate detection result.

Abstract: The present application provides a level shift circuit, an integrated circuit, and an electronic device. The level shift circuit comprises: an input module, configured to output a first control signal according to a first power supply voltage signal, first and second input voltages, inverted voltages of the first and second input voltages that received; a control voltage generation module, configured to receive the first control signal, and generate a plurality of node voltages according to the first control signal and a second power supply voltage signal; and output control modules, configured to generate first to fourth output signals according to the node voltages and the first power supply voltage signal, or generate fifth to eighth output signals according to the second power supply voltage signal and the node voltages.

Abstract: The present application provides a method for controlling an offset voltage in a display device, a display device and a storage medium. The method for controlling an offset voltage in a display device comprises: generating a chopper signal based on at least one of a data output control signal and a polarity inversion control signal; and, controlling, according the chopper signal, the polarity of an offset voltage of an operational amplifier in the display device, so that the offset voltage is equivalently eliminated within at least one of a design space range and a design time range. By using the control method of the present application, without using large-size transistors and providing more signals, the display effect can be ensured and the size of the chip can also be reduced.