Abstract: A display panel includes an array substrate having a plurality of pixel regions in multi-rows and multi-columns, a thin film transistor comprising a gate, a source, a drain and an active layer being provided in each of the pixel regions. Two gate lines are provided between two adjacent rows of pixel regions. Two adjacent columns of pixel regions constitute one pixel column group, and a data line is provided between two columns of pixel regions in the same one pixel column group. The array substrate further includes a pixel electrode, a common electrode and a common electrode line comprising a horizontal common electrode line parallel to the gate line wherein a projection of the horizontal common electrode line in a direction perpendicular to the display panel is not overlapped with projections of the drains of respective thin film transistors in the direction perpendicular to the display panel.