Abstract: A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node; an output sub-circuit configured to output signal under control of the first node; a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point.

Abstract: A drive control circuit is disclosed, and the drive control circuit is connected in series between a driving circuit and a first voltage terminal and forms a loop together. The drive control circuit comprises a current adjustment circuit and a control circuit. The current adjustment circuit controls a current in the loop according to a voltage signal difference between a voltage signal of a second node and a voltage signal of a first node. The control circuit controls the voltage signal of the second node according to the voltage signal of the first node, so that the current adjustment circuit controls the current in the loop during a start-up phase of the driving circuit.

Abstract: The present disclosure relates to a counter substrate and display panel. The counter substrate includes a base substrate, PS pattern layer and alignment film. A surface of the PS pattern layer away from the base substrate is a support surface, and the PS pattern layer includes: main PSs in a display area and a peripheral barrier wall in a non-display area. The peripheral barrier wall has an elongated-strip shape and has a same length direction as a corresponding display area side, the support surface of the peripheral barrier wall is closer to the base substrate than that of the main PS, and a distance between the support surfaces of the peripheral barrier wall and main PS in a thickness direction is a first distance. A ratio between a width of the support surface of the peripheral barrier wall and the first distance is less than 100.

Abstract: A touch substrate manufacturing method, for manufacturing a target touch substrate to be assembled with a display substrate, is provided. A size of an active display region of the display substrate is a first preset size. The method includes: providing a touch substrate to be processed having a second preset size, the second preset size being greater than the first preset size; and cutting, in at least one cutting direction, the touch substrate to be processed to obtain the target touch substrate, the cutting direction being parallel to an extending direction of a touch channel on the touch substrate to be processed. A manufacturing method for touch module, a touch substrate and a touch module are also provided.

Abstract: The present disclosure relates to a touch-control panel, including a touch-control layer arranged on the side of a display substrate having a display area and a peripheral area. The touch-control layer includes a touch-control electrode at least partially located in the display area and a peripheral wiring located in the peripheral area; the touch-control electrode includes a first touch-control electrode and a second touch-control electrode; the peripheral wiring includes a first wiring, a second wiring, a first shielding line and a second shielding line; the first shielding line is arranged outside the first wiring, the second wiring is arranged outside the first shielding line, and the second shielding line is arranged outside the second wiring.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: The present disclosure relates to a reflective electrode and an array substrate and a display device thereof. The reflective electrode includes a reflective conductive layer and a color compensation layer located on the reflective conductive layer. The reflective conductive layer has a first reflectivity to first light having a first wavelength and a second reflectivity to second light having a second wavelength. The first light and the second light are combined into white light. The first reflectivity is smaller than the second reflectivity. The color compensation layer is configured such that the reflective electrode has a third reflectivity to the first light and a fourth reflectivity to the second light. A ratio of an absolute value of a difference between the third reflectivity and the fourth reflectivity to the third reflectivity is smaller than 16.4%.

Abstract: The present disclosure relates to the field of display technology, and provides a wiring substrate, an array substrate, and a light emitting module. The wiring substrate includes a base substrate, a first metal wiring layer, and an insulating material layer stacked in sequence. The first metal wiring layer is provided with a plurality of drive leads extending along a first direction, and the insulating material layer is provided with a plurality of via holes exposing the drive leads. Through adjusting positions of the drive leads and positions of the via holes, the wiring substrate can be applied to different microchips, and used further to prepare different array substrates.

Abstract: Provided are a driving backplane and a method for manufacturing the same, a display device. The method includes: forming a first conductive pattern including signal lines; forming an insulating layer having via holes; forming a second conductive pattern including pairs of coupling electrodes; sequentially forming an inorganic material layer and an organic material layer; performing step exposure and developing on the organic material layer to form an intermediate pattern including a hollow-out portion, a completely-reserved portion and a half-reserved portion; the completely-reserved portion is thicker than the half-reserved portion, a thickness of the half-reserved portion is x times that of the inorganic material layer; etching the inorganic material layer and the intermediate pattern until a part of the inorganic material layer, corresponding to the hollow-out portion, is removed; an etching selection ratio of the inorganic material layer to the intermediate pattern is 1:y, 0<x?y.

Abstract: The disclosure discloses an array substrate and a preparation method thereof, a display panel and a display device. The array substrate includes: a substrate, and a first metal layer, a metal oxide layer and a second metal layer which are sequentially stacked and isolated from each other on the substrate; the first metal layer includes a light shading metal, a first electrode, and an anti-static line; the metal oxide layer includes a first active layer; the second metal layer includes a gate line and a second electrode; the gate line is connected with the anti-static line through a first TFT, one of the first electrode and the second electrode forms the source and drain electrodes of the first TFT, and the other forms the gate electrode of the first TFT; and the source is electrically connected with the gate line, and the drain is electrically connected with the anti-static line.

Abstract: Disclosed are a touch substrate and a preparation method thereof, and a touch apparatus. The touch substrate includes an electrostatic transmission layer, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer which are sequentially stacked, wherein the first conductive layer includes a first touch electrode, the second conductive layer includes a second touch electrode and a second dummy electrode which are insulated from each other, and the second dummy electrode is electrically connected to the electrostatic transmission layer by means of a via penetrating the first insulating layer and the second insulating layer; and/or, the first conductive layer further includes a plurality of first dummy electrodes insulated from one another, and the first dummy electrode and the first touch electrode are insulated from each other.

Abstract: A selection circuit, a method for controlling the selection circuit, and a multiplexing circuit are provided. The selection circuit includes N control circuits and M booster circuits. Control terminals of M control circuits among the N control circuits are coupled to output terminals of the M booster circuits, respectively, and first input terminals of the M booster circuits are coupled to receive M control signals among N control signals, respectively. Second input terminals of the M booster circuits are coupled to receive M boost signals respectively, and each booster circuit is configured to provide the received control signal to an output terminal of the booster circuit and increase a potential at the output terminal of the booster circuit by using the received boost signal.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output an output blanking output control signal; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal; a selection sub-circuit, having a first terminal connected to the second input sub-circuit, a second terminal connected to the first input sub-circuit, and a third terminal connected to a first node, configured to control a potential of the first node according to the display output control signal and the blanking output control signal; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node.

Abstract: A touch panel includes: a substrate; a bridging layer; an insulating layer; and a touch layer, including a first touch area and a border area surrounding the first touch area; the border area includes at least one second touch area, and the second touch area includes a plurality of button portions; a second shielding body is disposed between the second touch area and the first touch area; the border area further includes a bonding area for bonding with a driving circuit board; the second shielding body is provided with at least one wire groove, and at least one touch wire is coupled to the bonding area by passing through the wire groove; and the touch layer is disposed on a surface of the insulating layer away from the substrate, and at least two adjacent shielding units are coupled by the bridging layer.

Abstract: A display panel includes a first defining layer, a first recessed layer, a flat layer, and a pixel unit layer that are laminated on a base substrate in sequence. The pixel unit layer includes a plurality of sub-pixels. The first defining layer defines one or more defining regions on the base substrate, and the one or more defining regions corresponding to part or all of the plurality of sub-pixels. A surface of the first recessed layer in each defining region is recessed.

Abstract: A driving control circuit, a driving control method, and a display device are disclosed. The driving control circuit includes an input terminal, a power-down time acquisition circuit, an output terminal, and a switch circuit. The input terminal is configured to receive an input voltage; the power-down time acquisition circuit is configured to detect a power-down time period required for the input voltage to decrease to a lowest voltage, the power-down time period is used to generate a switch control signal; the output terminal is configured to output a voltage; and the switch circuit is configured to receive the input voltage and determine, according to the switch control signal, whether to be turned on to transmit the input voltage to the output terminal for output.

Abstract: An array substrate, a method for manufacturing the array substrate and a display device are provided. The array substrate includes: a base substrate, and a thin film transistor, a storage capacitor, and a lapping pattern for connecting the thin film transistor to the storage capacitor arranged on the base substrate; wherein the thin film transistor includes a semiconductor layer, a gate insulation layer, a gate electrode, an interlayer insulation layer, a source electrode and a drain electrode arranged sequentially in that order; the interlayer insulation layer includes at least two inorganic insulation layers and at least one organic insulation layer laminated one on another, and both a layer proximate to the base substrate and a layer distal to the base substrate in the interlayer insulation layer are the inorganic insulation layers.

Abstract: A display substrate and a fabrication method thereof, a display panel and a display device are provided. The display substrate includes pixels. Each of the pixels includes sub-pixels that emit light of different colors, each of the sub-pixels includes a light emitting element, and at least one of the sub-pixels further includes a color filter. The color filter of the at least one of the sub-pixels covers a portion of a light emitting region of the light emitting element of the at least one of the sub-pixels, and a color of the color filter of the at least one of the sub-pixels is the same as a color of light emitted by the light emitting element of the at least one of the sub-pixels.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: Disclosed is a shift register unit set, a gate driving circuit and a display apparatus, the shift register set including: cascaded n shift register units, and an ith stage of shift register unit in the shift register unit set includes: a first input sub-circuit and a second input sub-circuit, wherein the first input sub-circuit includes: a charging sub-circuit, a storing sub-circuit, an isolating sub-circuit, an output sub-circuit, a first electric leakage prevention sub-circuit configured to input an operation potential to the isolating sub-circuit under the control of the blanking pull-up control node, and a second electric leakage prevention sub-circuit configured to input the operation potential to a second electrode of the isolating transistor under the control of the first pull-up node, wherein there is an overlap among n composite output signals output by the n shift register units, n and i are positive integers, and 1?i?n.