Abstract: An apparatus for performing multi-tier domain pre-characterization for floating random walk capacitance extraction of a semiconductor structure includes a processor configured to recursively execute a floating random walk algorithm, over a plurality of points for a plurality of conductors, to permit determination of a potential at a plurality of points on a Gaussian surface around each of a plurality of conductors and determination of a coupling capacitance between the plurality of conductors, each iteration of the floating random walk algorithm comprising selection of a domain about an initial boundary point on the Gaussian surface of the respective one of the plurality of conductors and determination of a new boundary point on the new domain, from which a successive boundary point is selected with a corresponding successive domain centered thereabout, this process continuing until a corresponding successive domain terminates at a boundary having a known potential, whereupon the processor determines the pote

Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a noise compatible netlist, ensuring accurate DC behavior, and simulating the circuit using the synthesized netlist.

Abstract: An apparatus for extracting capacitances of arbitrarily oriented three-dimensional interconnects includes a processor configured to recursively execute a floating random walk algorithm over a plurality of points for a plurality of conductors, to permit determination of a potential at a plurality of points on a Gaussian surface around each conductor and determination of a coupling capacitance between each conductor. Each iteration includes selecting an initial domain centered about an initial boundary point on a Gaussian surface of an initial conductor, determining a new boundary point on the initial domain from which a successive domain centered about the new boundary point may be selected, and determining a corresponding successive boundary point on the successive domain, each iteration continuing until the new boundary point or the corresponding successive boundary point terminates on a boundary having a known potential. Each selected domain may be rotated to align with the nearest conductor.

Abstract: Systems and methods related to fast simulation of power delivery networks are described. A method is provided for simulating the time-domain responses of a plurality of points of a multi-layer power delivery network, comprising selecting a model of the power delivery network of a circuit, parsing the characteristic data describing the power delivery network, forming a circuit matrix relating to said circuit characteristic data, creating a preconditioner matrix with a specialized structure that allows solution by a Fast Transform solver, simulating the circuit using said circuit and preconditioner matrices by a computer, including a non-transitory computer readable storage medium and at least one processor, but preferably multiple processors, and reporting the responses at selected nodes and branches of the power delivery network.

Abstract: Presented herein are systems, methods, and devices for analyzing a circuit. A netlist is obtained and parsed, where the netlist describes the circuit having one or more branches and one or more nodes. A linear system describing the circuit is obtained and compressed using a hierarchical approach. Compression involves storing off-diagonal sub-blocks in a dense matrix in a low-rank format to reduce the density of the matrix. The linear system is then solved using an iterative operation. An initial guess is used for the voltage at each node and the current through each branch. After performing the first iteration, an initial estimate for the voltage and current is stored and used as the initial guess for the second iteration. The iterative operation is continued until the estimate for the voltage at each node and the current through each branch is sufficiently accurate.

Abstract: Systems and methods related to fast simulation of power delivery networks are described. A method is provided for simulating the time-domain responses of a plurality of points of a multi-layer power delivery network, comprising selecting a model of the power delivery network of a circuit, parsing the characteristic data describing the power delivery network, forming a circuit matrix relating to said circuit characteristic data, creating a preconditioner matrix with a specialized structure that allows solution by a Fast Transform solver, simulating the circuit using said circuit and preconditioner matrices by a computer, including a non-transitory computer readable storage medium and at least one processor, but preferably multiple processors, and reporting the responses at selected nodes and branches of the power delivery network.

Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a positive netlist having no controlled current or voltage sources, unstamping the synthesized positive netlist, and simulating the circuit using the unstamped synthesized positive netlist.

Abstract: Systems, computer-readable storage media, and methods of providing RLCK parasitic extraction for electronic design of integrated circuits are presented herein. For one implementation, the method includes: importing a simulator netlist extracted from the schematic file that simulates the IC, the simulator netlist providing nets and devices in the schematic; importing the layout file which represents the physical layout of the IC; generating from the layout file a connectivity list with connectivity points in the IC for connecting generated RLCK parasitics; extracting from the layout file an RLCK netlist for the connectivity points; generating from the layout data file and the connectivity list a cross-reference between the connectivity points and the nets and devices in the simulator netlist; from the cross-reference, simulator netlist, and RLCK netlists, update the simulator netlist to includes RLCK parasitics for the connectivity points in the IC; and output an indication of the updated simulator netlist.

Abstract: Apparatus and method for designing an electrical component including a processor and a user interface, enabling a user to input a desired characteristic of the electrical component, such as inductance or quality factor at an operating frequency for an integrated spiral inductor.