Abstract: A memory controller for use in a graphics system includes a dual-pipeline architecture that maximizes the utilization of a dual-banked graphics memory. The dual-pipeline architecture allows for accesses for each bank to be forwarded separately within the memory controller prior to transferring them to the dual-banked graphics memory. Processing hardware is shared between the pipelines of the memory controller to minimize hardware overhead. By grouping access according to the bank with which they are associated, an arbitrator of the memory controller can provide data references to a frame buffer memory in a more desirable order. In addition, the delays associated with accessing a bank may be minimized, since the bank addresses are available at both pipeline outputs before they require processing. Thus, while one bank is being accessed, preparations for accessing the second bank may be initiated.