Abstract: A slurry spraying mask includes a holding portion and a mask portion. The holding portion includes a holding portion opening. The mask portion includes a first layer and a second layer. The first layer includes a first tapered structure, the second layer includes a second tapered structure. The first tapered structure and the second tapered structure are arranged coaxially. A gap exists between the first layer and the second layer. The apex of the first tapered structure includes a first aperture, the apex of the second tapered structure includes a second aperture, and the second aperture is overlapped with the first aperture. The apex of the second tapered structure passes through the holding portion opening such that the mask portion is localized to the holding portion.

Abstract: A reaction chamber for vapor deposition apparatus, comprises a susceptor to carry substrates, a ceiling, an upper cavity, and protrusions. The ceiling comprises a front surface faces the substrates and comprises front convex parts and front concave parts with an interlaced arrangement to form a convex-concave surface. The ceiling also comprises a rear surface opposites to the front surface and comprises rear convex parts and rear concave parts corresponded to the front concave parts and the front convex parts respectively. The upper cavity opposites to the rear surface and separated to the rear convex parts to define a first flow channel. The protrusions are disposed in the rear concave parts and separated to a side wall and a bottom wall of the rear concave parts to define a second flow channel which is connected to the first flow channel to introduce a cooling fluid.

Abstract: A vapor phase film deposition apparatus comprises a susceptor where a plurality of substrates is placed thereon; and an opposing face member disposed opposite to the susceptor. The opposing face member includes a plurality of raised portions which protrude toward the susceptor to define at least one flow channel. A reaction gas flows through the flow channel and deposits on the plurality of substrates. At least one of the plurality of raised portions includes a heat insulation structure. The vapor phase film deposition apparatus further comprising a heating element disposed on one side of the susceptor, which is opposite to the opposing face member.

Abstract: An active wafer prober preheat-precool system comprises a wafer loading unit used to load at least one wafer; a probe card disposed corresponding to the wafer loading unit and used to test the wafer; a carrying mechanism including a central connector corresponding to the wafer loading unit and having a first opening, wherein the probe card is connected with the central connector and faces the wafer loading unit through the first opening; a peripheral connector having a second opening, wherein the central connector is detachably disposed inside the second opening; and a first temperature regulation unit disposed in the peripheral connector; and a control unit electrically connected with the first temperature regulation unit and controlling the first temperature regulation unit to adjust the temperature of the peripheral connector. The present invention also discloses a method for testing wafers.

Abstract: A semiconductor test apparatus includes a test chamber, a chuck and a refrigeration element. The chuck is arranged in the test chamber to fix a semiconductor element to be tested. The refrigeration element is connected to the test chamber to reduce a chamber ambient temperature of the test chamber from a first temperature to a second temperature. The foregoing semiconductor test apparatus is able to reduce the chamber ambient temperature of the test chamber to be equal to or lower than the specified test temperature.

Abstract: The invention relates to a probe card structure, which comprises printed circuit board structure with a first through hole, a center stiffener with a second through hole, a first probe head module with a first through hole set and a plurality of first probe pins, and a second probe head module provided with a plurality of second probe pins. The first probe head module and the second probe head module are respectively arranged on a lower surface and an upper surface of the printed circuit board structure, wherein those first probe pins are set on a periphery of an opening of the first through hole set; and a portion of the second probe head module penetrating the first through hole, the second through hole, and the first through hole set. The first and second probe head module integrated together can be utilized for 3D IC testing.

Abstract: A chemical vapor deposition apparatus comprises a ballast gas source and a mass flow controller, wherein the ballast gas source is arranged at an upstream side of a separating device, and the pressure in a reaction chamber is controlled by a flow rate of the ballast gas. Since the space between the reaction chamber and the node connected with the ballast gas source is small, a pressure response of the reaction chamber can be speeded up.

Abstract: A probe card for circuit-testing with fine pitch circuit including a testing PCB, a probe head, and a silicon interposer substrate is provided. The probe head has a plurality of probes provided with a fine pitch arrangement and held inside. The silicon interposer substrate is used for conveying signals between said probes and said test PCB. The interconnection of said silicon interposer substrate is fully-filled formed by utilizing the through-silicon via semiconductor fabrication process. A plurality of upper terminals and a plurality of lower terminals are respectively array-arranged on the top surface and the bottom surface of said silicon interposer substrate. The pitch between the upper terminals is larger than the pitch between the lower terminals and the pitch between adjacent lower terminals is equal to the fine pitch of the arrangement of probes.

Abstract: A system for manufacturing semiconductor epitaxy structure includes a deposition apparatus, a curvature monitor system and a control unit. The deposition apparatus is configured for sequentially depositing a buffer layer, a first epitaxy layer, an insertion layer, a second epitaxy layer on a substrate. The curvature monitor system is configured for monitoring a curvature value of the semiconductor epitaxy structure. The control unit is configured for controlling the deposition apparatus to stop depositing the buffer layer, the first epitaxy layer, the insertion layer and the second epitaxy layer according to the curvature value of the semiconductor epitaxy structure measured by the curvature monitor system. The above-mentioned system for manufacturing semiconductor epitaxy structure is able to effectively control the strain of the semiconductor epitaxy structure during growth. A method for manufacturing semiconductor epitaxy structure is also disclosed.

Abstract: The present invention relates to a printed circuit board of a probe card. The printed circuit board comprises a first side, a second side, a plurality of plated through holes and at least one electric barrier. The first side includes a plurality of first contacts and a plurality of second contacts respectively corresponding to the first contacts. The second side includes a plurality of third contacts respectively corresponding to the second contacts and a plurality of second-side traces extended to a predefined/specific region. The plated through holes penetrate through the first side and the second side, so that the third contacts are electrically connected to the second contacts. The at least one electric barrier is installed among at least two of the second side traces.

Abstract: A probe card for circuit-testing comprising a testing PCB, a probe head, and a silicon interposer substrate is provided. The probe head has a plurality of probes provided with a fine pitch arrangement and held inside. The silicon interposer substrate is used for conveying signals between said probes and said test PCB. The interconnection of said silicon interposer substrate is formed by utilizing the through-silicon via process. A plurality of upper terminals and a plurality of lower terminals are respectively array-arranged on the top surface and the bottom surface of said silicon interposer substrate. The pitch between the upper terminals is larger than the pitch between the lower terminals and the pitch between adjacent lower terminals is equal to the fine pitch of the arrangement of probes.

Abstract: A system for manufacturing semiconductor epitaxy structure includes a deposition apparatus, a curvature monitor system and a control unit. The deposition apparatus is configured for sequentially depositing a buffer layer, a first epitaxy layer, an insertion layer, a second epitaxy layer on a substrate. The curvature monitor system is configured for monitoring a curvature value of the semiconductor epitaxy structure. The control unit is configured for controlling the deposition apparatus to stop depositing the buffer layer, the first epitaxy layer, the insertion layer and the second epitaxy layer according to the curvature value of the semiconductor epitaxy structure measured by the curvature monitor system. The above-mentioned system for manufacturing semiconductor epitaxy structure is able to effectively control the strain of the semiconductor epitaxy structure during growth. A method for manufacturing semiconductor epitaxy structure is also disclosed.

Abstract: The invention relates to a printed circuit board structure, which comprises a first body, a second body and a sleeve. The sleeve is arranged between and connected with the first body and the second body so as to generate a differential height between the first body and the second body. Via the differential height are solved the problems of insufficient probe stiffness and poor wafer-sort quality, which is caused by decreasing the probe diameter to adapt to miniaturized chips.

Abstract: A test probe card structure includes a probe card and a connection circuit common plate. The probe card includes a probe substrate, A test circuit board is disposed between the probe substrate and the connection circuit common plate, The test circuit board has a lest circuit connection section attached to and electrically connected with a common circuit adaptation section of the connection circuit common plate. A circuit extension section is formed around the connection circuit common plate, which is all-channel electrically connectable between a tester and the teat circuit connection section. The connection circuit common plate serves to provide an all-channel test circuit convergence connection ability for the test circuit board so as to greatly minify the size of the test circuit board and lower the manufacturing cost of the probe card.

Abstract: A probe card structure adaptable to different test apparatuses of different specifications includes a probe card adapted to a first specification, a reinforcement member adapted to a second specification and a specification conversion interface unit disposed between the probe card and the reinforcement member. The probe card without the specification conversion interface unit can be directly mounted on a test apparatus of the first specification by means of a reinforcement member of the first specification to carry out the test process. Alternatively, the specification conversion interface unit can be combined with the probe card to convert the probe card from the first specification to the second specification. Accordingly, the probe card of the second specification can be mounted on a test apparatus of the second specification by means of the reinforcement member of the second specification to carry out the test process.

Abstract: A probe card for circuit-testing comprising a testing PCB, a probe head, and a silicon interposer substrate is provided. The probe head has a plurality of probes provided with a fine pitch arrangement and held inside. The silicon interposer substrate is used for conveying signals between said probes and said test PCB. The interconnection of said silicon interposer substrate is formed by utilizing the through-silicon via process. A plurality of upper terminals and a plurality of lower terminals are respectively array-arranged on the top surface and the bottom surface of said silicon interposer substrate. The pitch between the upper terminals is larger than the pitch between the lower terminals and the pitch between adjacent lower terminals is equal to the fine pitch of the arrangement of probes.

Abstract: An optoelectronic component with three-dimension quantum well structure and a method for producing the same are provided, wherein the optoelectronic component comprises a substrate, a first semiconductor layer, a transition layer, and a quantum well structure. The first semiconductor layer is disposed on the substrate. The transition layer is grown on the first semiconductor layer, contains a first nitride compound semiconductor material, and has at least a texture, wherein the texture has at least a first protrusion with at least an inclined facet, at least a first trench with at least an inclined facet and at least a shoulder facet connected between the inclined facets. The quantum well structure is grown on the texture and shaped by the protrusion, the trench and the shoulder facet.

Abstract: An electrode structure adapted for high applied voltage is provided, which comprises a conductive plate substrate and a covering layer disposed thereon such that a covering percentage of the covering layer over the conductive plate substrate is more than 50%. Since area of the conductive plate substrate covered by the covering layer is larger than the area exposed, the possibility of arcing is reduced and the breakdown voltage applied to the electrode structure may be increased.

Abstract: An upper electrode for use in a plasma processing chamber is provided, which includes a center segment and a plurality of outer segments. The outer segments are attached to the center segment to adjust the area of the overall electrode. Gas distribution holes may be selectively formed on the center and outer segments, or both. By adding or removing the outer segments and stacking layers, the dimension of the electrode, the area of gas spurting region and the thickness of the provided upper electrode may be adjusted.

Abstract: An optoelectronic component with three-dimension quantum well structure and a method for producing the same are provided, wherein the optoelectronic component comprises a substrate, a first semiconductor layer, a transition layer, and a quantum well structure. The first semiconductor layer is disposed on the substrate. The transition layer is grown on the first semiconductor layer, contains a first nitride compound semiconductor material, and has at least a texture, wherein the texture has at least a first protrusion with at least an inclined facet, at least a first trench with at least an inclined facet and at least a shoulder facet connected between the inclined facets. The quantum well structure is grown on the texture and shaped by the protrusion, the trench and the shoulder facet.