Abstract: Provided is an optical fiber array capable of alignment for a silicon photonics wafer testing system including a base, a lid, a plurality of fiber optics, and a plurality of marks. The base has a first endface and a plurality of grooves, and one lateral opening of each groove is located on the first endface. The lid has a second endface and is stacked onto the base to cover the grooves and portions of the fiber optics in the grooves and expose the lateral openings. The first endface, light emitting/receiving surfaces of the fiber optics, and the second endface are located on a same plane. The marks are respectively disposed on the first endface and the second endface and outside a range where the fiber optics are located. An alignment method of an optical fiber array is also provided.

Abstract: An optical coupling verification method is used in a silicon photonics wafer testing system including a wafer prober, an optical coupling actuator, an optical measurement instrument, and an integrated control module electrically connected to the wafer prober, optical coupling actuator, and optical measurement instrument. An optical fiber array is disposed on the optical coupling actuator on an optical path of the optical measurement instrument. The method includes: loading a verification kit into the wafer prober; and driving, by the integrated control module, an upward-facing camera of the wafer prober to be aligned with the optical fiber array. The integrated control module drives a downward-facing camera of the wafer prober to be aligned with the verification kit, obtains a relative position relation between the optical fiber array and the verification kit in the wafer prober, and performs optical coupling verification to obtain characteristics variation of light of the optical path.

Abstract: A silicon photonics wafer testing system includes a wafer prober, an optical coupling actuator, an optical measurement instrument, and an integrated control module. The wafer prober includes an upward-facing camera, a downward-facing camera, and a probe card. A silicon photonics wafer is adapted to be carried on a stage of the wafer prober. The probe card is disposed above the stage. At least one optical fiber array is adapted to be carried on a fiber holder of the optical coupling actuator. The optical fiber array is located on an optical measurement path of the optical measurement instrument. The integrated control module is electrically connected to the wafer prober, the optical coupling actuator, and the optical measurement instrument. A silicon photonics wafer testing method is also provided.

Abstract: A temperature detection system including a wafer, a plurality of sensing modules, and a probe is provided. The wafer has a plurality of dies. The sensing modules are adjacent to the dies, and each of the sensing modules includes a temperature sensor and a plurality of pads. The pads are electrically connected to the temperature sensor. The sensing modules transmit detection signals through the probe.

Abstract: A probe card monitoring system is adapted for any one of a probe card including a reinforcement frame and a printed circuit board or a prober including a head plate and a clamping mechanism, and includes at least one sensor and a control unit. The at least one sensor is disposed in one of the probe card and the prober to measure a distance between the probe card and the prober in at least one axial direction. The control unit is coupled to the at least one sensor and is configured to issue an alarm. A probe card monitoring method is also provided.

Abstract: The present invention provides a probe card. A module cap, on the probe card substrate, is designed to have a chute and the probe module can be installed on or uninstalled from the module cap via the chute. That simplifies the operations of assembling and disassembling the probe card and avoids positioning error.

Abstract: An adjustable supporting device including a circuit board, a first fixing module, an adjusting module, a second fixing module, and a supporting base is configured to support a test circuit module. The supporting base is positioned in a first opening of the circuit board, a second opening of the first fixing module, and a third opening of the adjusting module and abuts against the second fixing module and a carrier of the test circuit module. The supporting base includes a first portion abutting against the second fixing module, a second portion connected to a third portion, the third portion connected to a fourth portion, and the fourth portion abutting against the carrier. The first portion and the second portion adjust the parallelism between the test circuit module and a semiconductor element through contact, thereby adjusting the horizontal flatness of multiple contact points of the test circuit module.

Abstract: An injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a height-adjusting base, a reservoir, a first testing pipe, a cleaning pipe, a liquid-draining pipe, and an electrode rod. The reservoir is provided with a dropping port. The dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to the reservoir. The electrode rod penetrates through the reservoir and contacts and ionizes a testing liquid. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

Abstract: An adjustable supporting device including a circuit board, a first fixing module, an adjusting module, a second fixing module, and a supporting base is configured to support a test circuit module. The supporting base is positioned in a first opening of the circuit board, a second opening of the first fixing module, and a third opening of the adjusting module and abuts against the second fixing module and a carrier of the test circuit module. The supporting base includes a first portion abutting against the second fixing module, a second portion connected to a third portion, the third portion connected to a fourth portion, and the fourth portion abutting against the carrier. The first portion and the second portion adjust the parallelism between the test circuit module and a semiconductor element through contact, thereby adjusting the horizontal flatness of multiple contact points of the test circuit module.

Abstract: A temperature detection system including a wafer, a plurality of sensing modules, and a probe is provided. The wafer has a plurality of dies. The sensing modules are adjacent to the dies, and each of the sensing modules includes a temperature sensor and a plurality of pads. The pads are electrically connected to the temperature sensor. The sensing modules transmit detection signals through the probe.

Abstract: A probe card monitoring system is adapted for any one of a probe card including a reinforcement frame and a printed circuit board or a prober including a head plate and a clamping mechanism, and includes at least one sensor and a control unit. The at least one sensor is disposed in one of the probe card and the prober to measure a distance between the probe card and the prober in at least one axial direction. The control unit is coupled to the at least one sensor and is configured to issue an alarm. A probe card monitoring method is also provided.

Abstract: A testing substrate includes a first build-up structure and a ceramic substrate. The ceramic substrate is arranged on the first build-up structure. The first bonding interface between the first build-up structure and the ceramic substrate includes a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface. A manufacturing method of a testing substrate and a probe card are also provided.

Abstract: The present invention provides a probing system, which utilizes a suction nozzle to suck a wafer in probing. A relative distance between the suction nozzle and the probes can be adjusted according the conditions of the probing system, so the system extends the usage life.

Abstract: A testing substrate includes a first build-up structure and a ceramic substrate. The ceramic substrate is arranged on the first build-up structure. The first bonding interface between the first build-up structure and the ceramic substrate includes a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface. A manufacturing method of a testing substrate and a probe card are also provided.

Abstract: A testing substrate includes a substrate and a first build-up structure. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first conductive pattern. The first conductive pattern includes a plurality of conductive connectors, and each conductive connector penetrates the substrate from the first surface to the second surface of the substrate. The first build-up structure is arranged on the first surface. The first build-up structure has a second conductive pattern. The first conductive pattern is electrically connected to the second conductive pattern, and the size of the first conductive pattern is larger than or equal to the size of the second conductive pattern. A manufacturing method of the testing substrate and a probe card are also provided.

Abstract: An injection device is disclosed herein. The injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a base, a reservoir, a first testing pipe, a cleaning pipe and a liquid-draining pipe. The reservoir set on the base is provided with at least one connecting port and a dropping port, wherein the dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to at least one connecting port, wherein a first liquid is injected from the first testing pipe into the reservoir, and wherein the a cleaning liquid is injected from the cleaning pipe into the reservoir to clean the reservoir and the test area. The dropping port is utilized to drain off the first testing liquid and the cleaning liquid in the reservoir. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

Abstract: An injection device is disclosed herein. The injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a base, a reservoir, a first testing pipe, a cleaning pipe and a liquid-draining pipe. The reservoir set on the base is provided with at least one connecting port and a dropping port, wherein the dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to at least one connecting port, wherein a first liquid is injected from the first testing pipe into the reservoir, and wherein the a cleaning liquid is injected from the cleaning pipe into the reservoir to clean the reservoir and the test area. The dropping port is utilized to drain off the first testing liquid and the cleaning liquid in the reservoir. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

Abstract: A probe card includes at least two connection arrangements on a printed circuit board and a daughter board connected to the printed circuit board through one of the connection arrangements. The daughter board includes a plurality of cell modules, with each of the cell modules having a socket for receiving a device under test and each of the connection arrangements of the printed circuit board being connectable to each of predetermined daughter boards respectively.

Abstract: A CIS test probe card with an optic assembly is disclosed. At least one embodiment relates to the optic assembly being located close to the CIS test probe card to collimate a light before it is projected through the CIS test probe card to the wafer. At least one embodiment relates to a change in the geometric configuration of the hole(s) and the probe(s) in the CIS test probe card. Small holes corresponding to the CIS chips in a one-on-one fashion can be implemented, such that each small hole is located over a corresponding CIS chip.

Abstract: A CIS test probe card with an optic assembly is disclosed. At least one embodiment relates to the optic assembly being located close to the CIS test probe card to collimate a light before it is projected through the CIS test probe card to the wafer. At least one embodiment relates to a change in the geometric configuration of the hole(s) and the probe(s) in the CIS test probe card. Small holes corresponding to the CIS chips in a one-on-one fashion can be implemented, such that each small hole is located over a corresponding CIS chip.