Patents Assigned to Hestia Power Inc.
  • Patent number: 11869943
    Abstract: A silicon carbide semiconductor device, in particular a monolithically integrated trench Metal-Oxide-Semiconductor Field-Effect Transistor with segmentally surrounded trench Schottky diode, includes a semiconductor substrate, a trench Metal-Oxide-Semiconductor Field-Effect Transistor and a trench Schottky diode. The trench Schottky diode has a perpendicularly disposed trench extending in a first horizontal direction, a metal electrode filled into the trench, and a plurality of doped regions disposed segmentally and extending in a second horizontal direction around the trench. The first horizontal direction is substantially orthogonal to the second horizontal direction, a side wall and a bottom wall of the metal electrode in the trench forms a Schottky junction, and the current flowing from the metal electrode is restricted between adjacent doped regions.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: January 9, 2024
    Assignee: SHANGHAI HESTIA POWER INC.
    Inventors: Chien-Chung Hung, Kuo-Ting Chu, Chwan-Yin Li
  • Patent number: 11222971
    Abstract: The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 11, 2022
    Assignee: Shanghai Hestia Power Inc.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Fu-Jen Hsu, Kuo-Ting Chu
  • Patent number: 11184003
    Abstract: A silicon carbide power device is controlled by a driver and comprises a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to an increase of the gate-to-source voltage, or the source voltage increases according to a decrease of the gate-to-source voltage. Thus, a spike caused by a change of the gate-to-source voltage is suppressed, thereby suppressing the crosstalk phenomenon of the silicon carbide power device.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: November 23, 2021
    Assignee: SHANGHAI HESTIA POWER INC.
    Inventors: Fu-Jen Hsu, Chien-Chung Hung, Kuo-Ting Chu, Chwan-Ying Lee
  • Patent number: 11108388
    Abstract: A silicon carbide power device controlled by a driver and comprises a gate-to-source voltage and a source voltage, wherein the source voltage decreases according to an increase of the gate-to-source voltage, or the source voltage increases according to a decrease of the gate-to-source voltage. Thus, a spike caused by a change of the gate-to-source voltage is suppressed, thereby suppressing the crosstalk phenomenon of the silicon carbide power device.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 31, 2021
    Assignee: Shanghai Hestia Power, Inc.
    Inventors: Fu-Jen Hsu, Chien-Chung Hung, Kuo-Ting Chu, Chwan-Ying Lee
  • Patent number: 10497777
    Abstract: A semiconductor power device includes an n-type drift layer, a plurality of first p-doped regions, a plurality of n-doped regions, a plurality of second p-doped regions, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a plurality of source contacts. Each first p-doped region includes a first p-doped portion and a plurality of first p-doped arms extending outwards from the first p-doped portion. Each n-doped region includes an n-doped portion and a plurality of n-doped arms extending outwards from the n-doped portion.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 3, 2019
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee
  • Patent number: 10483389
    Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: an n-type substrate, an n-type drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 19, 2019
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
  • Patent number: 10418476
    Abstract: The present invention is related to a silicon carbide semiconductor device which employs a silicon carbide substrate to form an integrated device. The integrated device of the present invention comprises a metal oxide semiconductor field-effect transistor (MOSFET) and an integrated junction barrier Schottky (JBS) diode in an anti-parallel connection with the MOSFET.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: September 17, 2019
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee
  • Patent number: 10396774
    Abstract: An intelligent power component module operable to be driven by a negative gate voltage integrates a wide bandgap semiconductor power unit, an adjustment unit and a driving unit so as to adjust a voltage level of the driving unit by the adjustment unit. Accordingly, the wide bandgap semiconductor power unit, in a driven state, comprises a driving voltage level alternating between a positive and a negative voltage.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 27, 2019
    Assignee: Hestia Power Inc.
    Inventors: Chien-Chung Hung, Fu-Jen Hsu, Cheng-Tyng Yen, Chwan-Ying Lee
  • Patent number: 10020368
    Abstract: A silicon carbide (SiC) semiconductor element includes a semiconductor layer, a dielectric layer on a surface of the semiconductor layer, a gate electrode layer on the dielectric layer, a first doped region, a second doped region, a shallow doped region and a third doped region. The semiconductor layer is of a first conductivity type. The first doped region is of a second conductivity type and includes an upper doping boundary spaced from the surface by a first depth. The shallow doped region is of the second conductivity type, and extends from the surface to a shallow doped depth. The second doped region is adjacent to the shallow doped region and is at least partially in the first doped region. The third doped region is of the second conductivity type and at least partially overlaps the first doped region.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 10, 2018
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Hsiang-Ting Hung, Yao-Feng Huang, Chwan-Ying Lee
  • Patent number: 9761703
    Abstract: A wide bandgap semiconductor device with an adjustable voltage level includes a wide bandgap semiconductor power unit and a level adjusting unit. The wide bandgap semiconductor power unit includes a source terminal, to which the level adjusting unit is electrically connected. The level adjusting unit provides a level shift voltage via the source terminal to adjust a driving voltage level of the wide bandgap semiconductor power unit. By adjusting the driving voltage level of the wide bandgap semiconductor power unit using the level adjusting unit, the wide bandgap semiconductor device may serve as a high-voltage enhancement-mode transistor to achieve reduced costs and an increased switching speed.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: September 12, 2017
    Assignee: HESTIA POWER INC.
    Inventors: Fu-Jen Hsu, Chien-Chung Hung, Yao-Feng Huang, Cheng-Tyng Yen, Chwan-Ying Lee
  • Patent number: 9685552
    Abstract: A silicon carbide field effect transistor includes a silicon carbide substrate, an n-type drift layer, a p-type epitaxy layer, a source region, a trench gate, at least one p-type doped region, a source, a dielectric layer and a drain. The p-type doped region is disposed at the n-type drift layer to be adjacent to one lateral side of the trench gate, and includes a first doped block and a plurality of second doped blocks arranged at an interval from the first doped block towards the silicon carbide substrate. Further, a thickness of the second doped blocks does not exceed 2 um. Accordingly, not only the issue of limitations posed by the energy of ion implantation is solved, but also an electric field at a bottom and a corner of the trench gate is effectively reduced, thereby enhancing the reliability of the silicon carbide field effect transistor.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: June 20, 2017
    Assignee: Hestia Power Inc.
    Inventors: Chien-Chung Hung, Cheng-Tyng Yen, Hsiang-Ting Hung, Chwan-Ying Lee
  • Patent number: 9373713
    Abstract: A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 21, 2016
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Yao-Feng Huang, Hsiang-Ting Hung, Chwan-Ying Lee
  • Patent number: 9368650
    Abstract: A SiC junction barrier controlled Schottky rectifier includes a SiC substrate, a n-type drift layer, a p-type doping region, a plurality of junction field-effect regions, a first metal layer and a second metal layer. The drift layer is disposed on the SiC substrate. The junction field-effect regions are disposed in the drift layer and are surrounded by the p-type doping region. The first metal layer is disposed on the drift layer. The second metal layer is disposed at one side of the SiC substrate away from the drift layer. Through N circular regions and (N?1) inter-circle regions each connecting two of the circular regions, as well as geometric characteristics of the circular regions and the inter-circle regions, a leakage current of devices is effectively reduced and ruggedness is increased to improve an issue of a large leakage current of a conventional Schottky barrier diode.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: June 14, 2016
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
  • Patent number: 9246016
    Abstract: A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: January 26, 2016
    Assignee: HESTIA POWER INC.
    Inventors: Cheng-Tyng Yen, Chien-Chung Hung, Chwan-Ying Lee, Lurng-Shehng Lee
  • Patent number: 9018640
    Abstract: A silicon carbide power device equipped with termination structure comprises a silicon carbide substrate, a power element structure and a termination structure. The silicon carbide substrate contains a drift layer which has a first conductivity and includes an active zone and a termination zone. The power element structure is located in the active zone. The termination structure is located in the termination zone and has a second conductivity, and includes at least one first doped ring abutting and surrounding the power element structure and at least one second doped ring surrounding the first doped ring. The first doped ring has a first doping concentration smaller than that of the second doped ring and a first doping depth greater than that of the second doped ring, thereby can increase the breakdown voltage of the silicon carbide power device.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 28, 2015
    Assignee: Hestia Power Inc.
    Inventors: Chien-Chung Hung, Cheng-Tyng Yen, Lurng-Shehng Lee, Chwan-Ying Lee
  • Publication number: 20150102362
    Abstract: A silicon carbide power device equipped with termination structure comprises a silicon carbide substrate, a power element structure and a termination structure. The silicon carbide substrate contains a drift layer which has a first conductivity and includes an active zone and a termination zone. The power element structure is located in the active zone. The termination structure is located in the termination zone and has a second conductivity, and includes at least one first doped ring abutting and surrounding the power element structure and at least one second doped ring surrounding the first doped ring. The first doped ring has a first doping concentration smaller than that of the second doped ring and a first doping depth greater than that of the second doped ring, thereby can increase the breakdown voltage of the silicon carbide power device.
    Type: Application
    Filed: March 4, 2014
    Publication date: April 16, 2015
    Applicant: Hestia Power Inc.
    Inventors: Chien-Chung Hung, Cheng-Tyng Yen, Lurng-Shehng Lee, Chwan-Ying Lee