Abstract: A method for making an IC package preferably includes providing a mold including first and second mold portions, and wherein the first mold portion carries a mold protrusion defining an IC-contact surface with peripheral edges and a bleed-through retention channel positioned inwardly from the peripheral edges. The method also preferably includes closing the first and second mold portions around the IC and injecting encapsulating material into the mold to encapsulate the IC and make the IC package having an exposed portion of the IC adjacent the mold protrusion. Morever, the bleed-through retention channel retains any encapsulating material bleeding beneath the peripheral edges of the IC contact surface, and prevents the encapsulating material from reaching further onto the exposed portion of the IC. The method may also include releasing the IC package with the exposed portion from the mold.

Abstract: An IC package preferably includes an IC and encapsulating material surrounding the IC, with the encapsulating material having an opening therein to define an exposed portion of the IC. Vestigial portions of encapsulating material may be left on the exposed portion of the IC and spaced inwardly from a periphery of the opening based upon molding using a mold protrusion which includes a bleed-through retention channel positioned inwardly from peripheral edges. The channel collects and retains any bleed-through of the encapsulating material. The IC package may further include a leadframe carrying the IC. The leadframe may include a die pad, finger portions, and a plurality of die pad support bars. The die pad may be downset below a level of the finger portions. Each of the die pad support bars may be resiliently deformed to accommodate the downset of the die pad. Low stress encapsulating material and adhesive may also be included in the IC package.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip mounted on a substrate by a plurality of solder bumps. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip that is mounted on a substrate by a reflow process and by a plurality of solder bumps. At least one standoff is located between the circuit chip and the substrate to maintain a distance between the circuit chip and the substrate during the reflow process. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip, the standoffs and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate.

Abstract: A semiconductor device package includes a carrier substrate molded of a non-laminate material. A plurality of conductive metal balls are molded within the non-laminate carrier substrate to provide an electrical connection between opposite sides of the substrate. The conductive metal balls provide conductive columns through the substrate for electrically connecting a chip mounted on one side of the substrate to solder balls on an opposite side of the substrate for mounting the package on a printed circuit board. The conductive columns eliminate the need for via holes which are used in known packages. The package with conductive columns provides a more compact, more precise, and lower cost package which is less susceptible to moisture damage than the known packages employing via holes.

Abstract: A transfer molded PC card standard or small form factor card electronic package includes a substrate that has an integrated circuit package thereon and an electrical connector along a side of the substrate. In addition, an upper cover extends over at least a portion of the substrate and the electrical connector. A lower cover extends over at least a portion of the substrate and the electrical connector and a transfer molded encapsulant covers the substrate and a portion of the upper cover and the lower cover. The portion of the upper cover and the lower cover are covered by the encapsulant and includes a first flange attached to a portion of a periphery of the upper cover and a second flange that is attached to a portion of the periphery of the lower cover.

Abstract: An integrated circuit chip package according to the present invention includes an integrated circuit chip mounted on a substrate by a plurality of solder bumps. A mold compound is used for underfilling air gaps between the chip and the substrate. The integrated circuit chip package is formed by placing the chip and substrate within a mold cavity and pressing a transfer mold compound into the mold cavity. Air spaces between the integrated circuit chip and the substrate are underfilled by the mold compound as it is pressed in between the integrated circuit chip and the substrate. Air is allowed to escape from between the chip and the substrate during the underfilling through a vent which extends through the substrate. The underfilling material may also be used to encapsulate the chip at the same time that underfilling is performed.

Abstract: A semiconductor device package includes a carrier substrate molded of a non-laminate material. A plurality of conductive metal balls are molded within the non-laminate carrier substrate to provide an electrical connection between opposite sides of the substrate. The conductive metal balls provide conductive columns through the substrate for electrically connecting a chip mounted on one side of the substrate to solder balls on an opposite side of the substrate for mounting the package on a printed circuit board. The conductive columns eliminate the need for via holes which are used in known packages. The package with conductive columns provides a more compact, more precise, and lower cost package which is less susceptible to moisture damage than the known packages employing via holes.

Abstract: A method for making multi-tier laminate substrates for electronic device packaging is provided wherein a spacing mechanism is used to protect the bond fingers of a trace on a lower tier of the laminated substrate when a milling bit is used to cut an opening above a die cavity in the multi-tier substrate.

Abstract: A printed wiring board with either a pin grid array, a ball grid array, a land grid array, etc. of electrical contacts is prepared with a heat sink attached in the usual manner. A passage is provided either in the printed wiring board or in the heat sink so that during the transfer molding process, fluid molding compound passes latitudinally under the heat sink into a cavity below the heat sink. The mold is provided with a biased plug that exerts pressure on the heat sink or printed wiring board to prevent molding compound from covering the heat sink. The biased plug also accommodates variations in the thickness of the printed wiring board.

Abstract: A printed wiring board with either a pin grid array, a ball grid array, a land grid array, etc. of electrical contacts is prepared with a heat sink in the usual manner. A passage is provided either in the printed wiring board or in the heat sink so that during the transfer molding process, fluid molding compound passes latitudinally under the heat sink into a cavity below the heat sink to encapsulate the package.

Abstract: A multi-tier laminate substrate with an internal heat spreader and method for making a multi-tier laminate substrate with an internal heat spreader for electronic device packaging are provided wherein a spacing mechanism is used to protect the bond fingers of a trace on a lower tier of the laminated substrate when a milling bit is used to cut an opening above a die cavity in the multi-tier substrate.

Abstract: A method for transfer molding a standard electronic package and an apparatus resulting from such method. A seal is formed between a portion of the mold platens of the mold and a portion of a printed circuit board adjacent to electrical contacts along at least one side of the printed circuit board. After the apparatus is removed from the mold, a protective cap is placed over the electrical contacts.

Abstract: A printed wiring board with either a pin grid array, a ball grid array, a land grid array, etc. of electrical contacts is prepared with a heat sink in the usual manner. A passage is provided either in the printed wiring board or in the heat sink so that during the transfer molding process, fluid molding compound passes latitudinally under the heat sink into a cavity below the heat sink to encapsulate the package.

Abstract: A method is disclosed for making multi-tier laminate substrates for electronic device packaging including providing a first laminating layer and a second laminating layer, each having a trace on a first side. These layers are laminated with a spacer layer and dielectric layers. A window is made in each of the spacer and the dielectric layers. After laminating the layers together, vias are formed. Then an opening is made in the first laminating layer that corresponds to the window openings in order to produce a cavity in the laminated structure for placing an electronic device therein.

Abstract: A printed wiring board with either a pin grid array, a ball grid array, a land grid array, etc. of electrical contacts is prepared with a heat sink attached in the usual manner. A passage is provided either in the printed wiring board or in the heat sink so that during the transfer molding process, fluid molding compound passes latitudinally under the heat sink into a cavity below the heat sink. The mold is provided with a biased plug that exerts pressure on the heat sink or printed wiring board to prevent molding compound from covering the heat sink. The biased plug also accommodates variations in the thickness of the printed wiring board.

Abstract: A multi-tier laminate substrate with an internal heat spreader and method for making a multi-tier laminate substrate with an internal heat spreader for electronic device packaging are provided wherein a spacing mechanism is used to protect the bond fingers of a trace on a lower tier of the laminated substrate when a milling bit is used to cut an opening above a die cavity in the multi-tier substrate,.