Abstract: A method is described for automatic generation of join graphs for relational database queries. The method includes marking instances of tables in a hierarchical representation of a database schema according to a selection procedure that processes tables in an input list having single occurrences in the hierarchical representation, multi-dimensional tables in the input list having multiple occurrences in the hierarchical representation, one-dimensional tables in the input list having multiple occurrences in the hierarchical representation that reference the multi-dimensional tables and have one of the multi-dimensional tables as a parent in the hierarchical representation, and any remaining one-dimensional tables in the input list having multiple occurrences in the hierarchical representation. The hierarchical representation is configured using expert knowledge of the database usage.

Abstract: A software development tool employing workflows for developing user interactive programs is described. The tool includes means for displaying a workspace on a computer screen, and means for displaying objects on the computer screen that are individually selectable to be placed and coupled together in the workspace to define a workflow for a user interactive program. Several objects have interactively alterable operation parameters. One object performs an interactively alterable switch function for directing data flow within the workflow. Another object facilitates branch processing according to a user indicated selection from displayed information generated by the user interactive program. Another object facilitates assigning a name to an input port of another object so that data may be directly provided to that input port. Another object prompts a user for input when a condition is met while executing the user interactive program.

Abstract: A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of the fault sources from the failure signatures; generating aggregate device test data from test data of a device for the preselected tests; generating aggregate matches by comparing the aggregate failure signatures with the aggregate device test data; and determining fault sources for device failures by comparing the test data of the device with ones of the failure signatures of fault sources corresponding to the aggregate matches. An apparatus configured to perform the method comprises at least one circuit.

Abstract: A method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout is described. Monte Carlo simulation generates simulated defects for an integrated circuit layout. Vertices significantly encroached by the simulated defects are identified. Information of predefined sets of vertices associated with individual nets including at least one of the identified vertices is retrieved. Failures resulting from the simulated defects are indicated only if all elements of at least one of the predefined sets of vertices are one of the identified vertices. The predefined sets of vertices are determined prior to circuit area analysis by extracting nets from an integrated circuit layout, and determining the predefined sets of vertices for individual nets such that the net fails only if all elements of individual of the predefined sets of vertices are significantly encroached by simulated defects.

Abstract: A method for determining the number of redundancy units to employ in a memory integrated circuit. The critical areas for faults on each process layer in the integrated circuit for a range of defect sizes, and the signatures of the electrical responses of faulted circuits to input test stimuli are determined. A statistical frequency distribution for both the signatures for a ratio of defect sizes on each of the process layers, and for the occurrences of selected combinations of the signatures are determined. A ratio of the signature distribution for different numbers of redundancy units, and the die area for each of the different numbers of redundancy units are determined. The number of usable die per wafer is determined from the signature distribution and the die area. A level of redundancy that maximizes the number of usable die per wafer is selected.

Abstract: A method for testing an integrated circuit wafer is described, wherein the wafer has a first plurality of dice defined thereon, and at least one die has at least one known defect. The method comprises the steps of selecting for testing a first die having a known defect; analyzing connectivity information and defect information relating to the first die, determining, based upon the analysis, a probability of failure for each known defect on the first die, and modifying the sequence of tests performed on the first die so that at least one test which directly relates to a known defect is performed prior to performing tests which are unrelated to a defect.

Abstract: A method for managing stepper operations required during the manufacturing of an integrated circuit die having at least one known defect, as determined by inspection, comprises the steps of determining, based upon an analysis of the connectivity and defect information relating to the die having at least one known defect a probability of failure to each at least one known defect and eliminating from stepper operations any die having at least one fatal defect.

Abstract: A memory device which tests the memory array under typical operating conditions. In one embodiment, the memory device incorporates a heating element to heat the memory array to a predetermined operating temperature, and a BIST (built-in self test) unit to test the memory array at the predetermined operating temperature. This may advantageously provide a method for detecting and repairing faulty memory locations that would not normally test faulty under initial power-up conditions. Broadly speaking, the present invention contemplates a memory device which comprises a memory array and a heating element on a substrate. The memory array is configured to receive a read/write signal on a read/write line, configured to receive an address on an address bus, configured to provide data to a data bus when the read/write signal indicates a read operation, and configured to store data from the data bus when the read/write signal indicates a write operation.

Abstract: A system and method for using a BIST generator and a BIST compactor to characterize the propagation delay time of a high-speed embedded cores and integrated circuits in general. In one embodiment, an external clock is provided having a positive edge and a negative edge. The BIST generator and test compactor is configured to apply a set of test inputs to the integrated circuit in response to the positive edge, and the BIST compactor is configured to latch a set of outputs from the integrated circuit in response to the negative edge, and determine if the set of outputs represent a valid test result. The validity determination is monitored, and as long as the test result is valid, it is determined that the propagation delay time is less than the time interval between the positive and negative transitions. The propagation delay time can then be measured by reducing the time interval until invalid test results appear.