Abstract: In exemplary aspects of optimizing data centers, historical data corresponding to a data center is collected. The data center includes a plurality of systems. A data center representation is generated. The data center representation can be one or more of a schematic and a collection of data from among the historical data. The data center representation is encoded into a neural network model. The neural network model is trained using at least a portion of the historical data. The trained model is deployed using a first set of inputs, causing the model to generate one or more output values for managing or optimizing the data center using supplemental indicators.

Abstract: A storage drive adapter may comprise an adapter board, which may include a first and second carrier module interface to removably engage with a first and a second storage drive carrier module, respectively. The adapter board may further include a dual ported storage drive connector to engage with a complementary storage drive bay interface. The dual ported storage drive connector may include a first port to provide a first signal path from the complementary storage drive bay interface to the first carrier module interface. Similarly, the dual ported storage drive connector may also include a second port to provide a second signal path from the complementary storage drive bay interface to the second carrier module interface.

Abstract: An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

Abstract: Examples of instruction generation for validation of processor functionality are described. In an example, a validation instruction to be inserted in an instruction stream is selected. The validation instruction being generated based on an instruction set architecture of a processor-under-test (PUT). It is identified whether a hardware register of the PUT, is available for storing an outcome of execution of the validation instruction by the PUT. The validation instruction is inserted in the instruction stream, in response to identifying that the hardware register is available for storing the outcome. A set of data backup instructions is inserted in the instruction stream, in response to identifying that the hardware register is unavailable for storing the outcome. The set of data backup instructions is to store respective register values of each of the plurality of hardware registers in a primary memory.

Abstract: Examples herein relate to identifying a soft failure at member within a cluster dedicated to a microservice. Examples disclose identifying a statistical evaluation for each member within the cluster. Based on the statistical evaluation, identifying a soft failure among one of multiple members within the cluster. In response to the identification of the soft failure at one of the members within the cluster, performing an action.

Abstract: Example implementations disclosed herein include techniques for a ready only bufferpool for use in local nodes of a multi-node computing system. Read only transactions executed by a processor can reference a ready only bufferpool resident in a VRAM on the same node. If the desired data page is in the bufferpool the transaction can immediately read data records from the cached data pages. If the desired data page is not in the bufferpool, then the transaction can cause a copy of a corresponding data page in a secondary memory to be installed in the bufferpool. The bufferpool can include more than one copy of a data page simultaneously to handle and prevent cache line misses. Data page are dropped from the bufferpool based on an incrementing per data page counter.

Abstract: A map-reduce compatible distributed file system that consists of successive component layers that each provide the basis on which the next layer is built provides transactional read-write-update semantics with file chunk replication and huge file-create rates. Containers provide the fundamental basis for data replication, relocation, and transactional updates. A container location database allows containers to be found among all file servers, as well as defining precedence among replicas of containers to organize transactional updates of container contents. Volumes facilitate control of data placement, creation of snapshots and mirrors, and retention of a variety of control and policy information. Also addressed is the use of distributed transactions in a map-reduce system; the use of local and distributed snapshots; replication, including techniques for reconciling the divergence of replicated data after a crash; and mirroring.

Abstract: A programmable integrated circuit may include logic, signal select hardware, programmable signal analysis hardware, an embedded microcontroller, and a hardware interface. The logic performs one or more functions and outputs a plurality of signals. The signal select hardware selects one or more of the signals output from the logic. The programmable signal analysis hardware analyzes the selected signals to produce diagnostic data. The embedded microcontroller receives the diagnostic data from the programmable signal analysis hardware and may reconfigure the logic based on the diagnostic data. The hardware interface connects the programmable signal analysis hardware and the embedded microcontroller to transport the diagnostic data.

Abstract: Examples relate to provisioning and activating hardware devices. In one example, a computing device may receive a request for a hardware resource; identify, in response to the request, a new hardware resource having hardware attributes indicating at least one capability of the new hardware resource; determine, based on the hardware attributes, a hardware template for provisioning the new hardware resource; configure the new hardware resource using the hardware template; and activate the new hardware resource in a cluster of at least one hardware device.

Abstract: Example implementations relate to determining whether network invariants are violated by flow rules to be implemented by the data plane of a network. In an example, a verification module implemented on a device receives a flow rule transmitted from an SDN controller to a switch, the flow rule relating to an event. The module determines whether the flow rule matches any of a plurality of network invariants cached in the device. If determined that the flow rule matches one of the plurality of network invariants, the verification module determines whether the flow rule violates the matched network invariant. If determined that the flow rule does not match any of the plurality of network invariants, the verification module (1) reports the event associated with the flow rule to a policy management module, (2) receives a new network invariant related to the event from the policy management module, and (3) determines whether the flow rule violates the new network invariant.

Abstract: In some examples, a non-transitory machine-readable medium can include instructions executable by a processing resource to: monitor a quantity of interactions between a plurality of user interfaces with an embedded device, determine when the quantity of interactions with the embedded device exceeds a threshold, send a slow-down message to a portion of the plurality of user interfaces in response to the interactions with the embedded device exceeding the threshold, and restrict a portion of the quantity of interactions with the embedded device when the quantity of interactions continues to exceed the threshold for a quantity of time after the slow-down message was sent to the portion of the plurality of user interfaces.

Abstract: Systems and methods disclosed herein host bus adapter (HBA) drivers to detect when execution of input/output (I/O) commands in urgent-priority queues is being delayed due to processing of I/O commands in lower-priority queues in NVMe subsystems, automatically identify which the lower-priority queue that is causing the delay, and mitigate the delay by throttling and migrating the lower-priority queue to the control of a controller that applies an arbitration mechanism other than weighted round robin.

Abstract: An example device in accordance with an aspect of the present disclosure includes a base to be mounted to a system board. A wicking region at the base is to wick adhesive into the wicking region to seal the base to the system board.

Abstract: Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.

Abstract: A computer implemented method comprises receiving an ethernet frame on an access port of a source switch in a switch fabric, the ethernet frame comprising a source media access control (SMAC) address and a destination media access control (DMAC) address, in response to a determination that the destination media access control address is not programmed into a media access control table of the source switch sending a destination lookup failure (DLF) message to a control plane associated with the switch, the destination lookup failure (DLF) message indicating that the destination media access control address received with the frame is not programmed into a media access control table of the source switch, and in response to a determination that the destination media access control address is programmed into a media access control table of at least one switch of the plurality of additional switches in the switch fabric, initiating a sequenced path setup on the source switch.

Abstract: A method for restricting write access to a non-volatile memory. The method includes receiving a request to write to a protected location in the non-volatile memory and determining whether the protected location is in a write-protected state. If the protected location is not in a write-protected state, the method includes writing data indicated by the request to the protected location. If the protected location is in a write-protected state, the method includes rejecting the request. The protected location stores a validation key to validate the contents of another portion of the non-volatile memory.

Abstract: Examples herein relate to devices having substrates with selective airgap regions for mitigating defects resulting from heteroepitaxial growth of device materials. An example device may include a first semiconductor layer disposed on a substrate. The first semiconductor layer may have a window cut through a face, where etching a selective airgap region on the substrate is enabled via the window. A second semiconductor layer may be heteroepitaxially grown on the face of the first semiconductor layer so that at least a portion of the second semiconductor layer is aligned over the selective air gap region.

Abstract: In example implementations, an apparatus includes a plurality of nodes, a pump coupled to the plurality of nodes and a connection network. In one example, each one of the plurality of nodes may store a value. The pump provides energy to the each one of the plurality of nodes. The connection network may include a two dimensional array of elements, wherein each group of the two dimensional array of elements is in communication with a respective one of the plurality of nodes, wherein the connection network may be tuned with parameters associated with encoding of an Ising problem. The connection network may process the value stored in each one of the plurality of nodes. The Ising problem may be solved by the value stored in each one of the plurality of nodes at a minimum energy level.

Abstract: A convolutional neural network system includes a first part of the convolutional neural network comprising an initial processor configured to process an input data set and store a weight factor set in the first part of the convolutional neural network; and a second part of the convolutional neural network comprising a main computing system configured to process an export data set provided from the first part of the convolutional neural network.