Abstract: A method for detecting thread switch conditions provides first and second scoreboard bits for each register in a register file. The first scoreboard bit associated with a register is set when a load is generated to return data to the register. The second scoreboard bit is set if the load misses in a selected processor cache. Register read instructions are monitored, and a thread switch condition is indicated when a register read instruction to the register is detected while its first and second scoreboard bits are set.
Type:
Grant
Filed:
December 31, 1997
Date of Patent:
August 7, 2001
Assignees:
Intel Corporation, Hewlette Packard
Inventors:
Harshvardhan Sharangpani, Rajiv Gupta, Judge K. Arora