Abstract: A system and process for recompacting digital storage space involves continuously maintaining a first log of free storage space available from multiple storage regions of a storage system such as a RAID system, and based on the first log, maintaining a second log file including a bitmap identifying the free storage space available from a given storage chunk corresponding to the storage regions. Based on the bitmaps, distributions corresponding to the storage regions are generated, where the distributions represent the percentage of free space available from each chunk, and a corresponding weight is associated with each storage region. The storage region weights may then be sorted and stored in RAM, for use in quickly identifying a particular storage region that includes the maximum amount of free space available, for recompaction.

Abstract: A method for managing persistent file handles includes starting an expiry timer and creating a Persistent File Handle (PHDL) container for storing extended file attributes including, a generation number (GN), a share GN (SGN), a previous SGN, and a timeout max value for an expiry timer, where a SGN is a timestamp of a volume migration or an online creation in relation to the expiry timer. The method additionally includes creating a PHDL iterator to update the SGNs for every volume exported to clients, volumes created online or for a restarting of a network-share service on a server. The method further includes triggering a clean-up of stale PHDL containers from a server memory based on a difference of the new SGN and the previous SGN being greater than the timeout maximum number else preserving the PHDL object container and updating the well-known key value.

Abstract: A method for managing file system memory includes starving an initial metadata memory area of a storage pool created for a file system transaction including cache data and log data. The method also includes determining on a transactional basis a ratio of metadata memory use to cache data use and an available unused portion of cache data memory replaceable in predetermined slab increments in the cache data. The method additionally includes shrinking transactionally the cache data per the slab increments based on the ratio via cleaning the cache data slabs and attaching the cache data slabs to the metadata memory area for temporary metadata use. The method further includes replacing the cache data slabs from the metadata memory area to the cache data based on a completion of the file system transaction. The slabs vary 5% to 10% or any arbitrary percentage of metadata space to cache data space.

Abstract: A method, system and a computer program product for managing file system memory includes a module configured to implement a separate replacement policy and a separate index for a persistent second level adaptive replacement cache (L2ARC) logically part of a first level ARC. The system also includes a module configured to cluster compressed chunks of data on multiple physical devices via aligning the clusters of data chunks on a byte boundary basis on each of the devices. The method additionally includes a module configured to create a storage pool allocator (SPA) to track the compressed and packed chunks on the multiple devices via an attached active page and attached multiple closed pages. The method further includes re-adding an evicted data from the L2ARC to an active page to be written again thereto based on a configurable threshold number of hits to data in the L2ARC via an L2ARC hit counter.

Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.

Abstract: A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.

Abstract: A method for producing a substantially planar surface for semiconductor processing to improve lithography, planarization, and other process steps that benefit from a flat substrate. The method includes depositing a first alloy to form a first layer on a substrate. The first layer has a center high deposition, meaning the height in the center of the substrate is higher than the height at the edges of the substrate. The method further includes depositing a second alloy on the first layer to form a second layer. The first alloy has a different composition than the second alloy. In such a method the net deposition is substantially planar reducing or eliminating deposition induced long-range distortions that might occur across a substrate.

Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.

Abstract: A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: A method and system for generating a reference voltage are disclosed. The reference voltage is generated by generating a voltage VRIGHT using a first transistor and generating a voltage VBIAS using a second transistor. The gates of the two transistors are connected to a common node VREF, but the loads of the transistors have different resistances. At least one differential pair is used to detect a difference between voltages VRIGHT and VBIAS. VREF is forced to a value at which the source-drain currents in each of the transistors is equal. The transistors sued are NMOS transistors.

Abstract: The present invention is a means and a method for manufacturing large three dimensional memory arrays. The present invention is a means and a method for addressing the WL and BL resistance by creating arrays having not only large plane conductors for each of the memory layers (WLs) but also for the opposite polarity common layer (BL). The present invention is also a means and a method to form via interconnections between the substrate logic and the respective layers of a multidimensional array. The present invention is also a way to operate an array in which the select device is unipolar but the array is above to be operated in a bipolar way. This facilitates a bipolar operation for memory cell technologies such as Resistive RAM (e.g., RRAM, ReRAM and Memresistors).

Abstract: A method for fabricating 3-D cross-point memory arrays, and more particularly to fabricating phase change memory (PCM) and resistive RAM (ReRAM or RRAM) 3-D memory arrays having a cell size footprint of 4F2. The method for forming a plurality of layers of memory cells using a limited number of photolithographic patterning steps is applicable to memory devices having single or multiple storage bits per cell, such as cells having anywhere from one to eight bits per cell or more. These bits are stacked three dimensionally and include memory cells based on phase change material, on resistive change material, on magnetic field alignment, on mechanical switching, and on other memory cells based on other information storage technologies.

Abstract: In various embodiments, a memory cell for storing two or more bits of information includes two series-connected memory storage elements composed of programmable materials having different melting points, enabling independent programming of the storage elements via different current pulses.

Abstract: In various embodiments, a memory storage element for storing two or more bits of information is formed by connecting two resistive change elements in series whereby the first resistive change element is made of a first material and the second resistive change element is made of a second material and the melting point of the first resistive change element material is greater than the melting point of the second resistive change element material such that the set and reset states of the two elements can be written and read.

Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.

Abstract: The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F.sup.2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

Abstract: In various embodiments, quench switches are utilized within a cross-point memory array to minimize parasitic coupling in lines proximate selected lines.

Abstract: The present invention is a means and method for constructing and operating a 3-D array and, more particularly, a 3-D memory array. This array can be manufactured as a monolithic integrated circuit at low cost by virtue of the limited number of steps per layer of memory elements. The low number of steps results by having the storage elements separated by a resistive component as opposed to an active component. The 3-D array is in essence, an array of 2-D resistive arrays (row-planes) having a long dimension (typically along the rows) and a short dimension (typically in the direction of the stacked layers). Any one row-plane can be isolated from the rest and be accessed independently from all of the other row-planes in the 3-D array. This makes it possible to operate and analyze a single row-plane as a mostly stand-alone circuit. The present invention lends itself to single bit accesses as well as simultaneous multiple bit accesses.

Abstract: A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. Each switch has at least three terminals and a cross-sectional area less than 6F2.