Abstract: A method for cache management in a hyperconverged infrastructure (HCI). The HCI includes a plurality of physical nodes (PNs). The method includes receiving a primary plurality of input/output (I/O) requests at a plurality of virtual machines (VMs), allocating a plurality of local caches (LCs) and a plurality of remote caches (RCs) to the plurality of VMs, receiving a secondary plurality of I/O requests at the plurality of VMs, and serving the secondary plurality of I/O requests. Each of the plurality of VMs runs on a respective corresponding PN of the plurality of PNs. The plurality of LCs and the plurality of RCs are allocated based on the primary plurality of I/O requests. The secondary plurality of I/O requests is served based on the plurality of LCs and the plurality of RCs.

Abstract: A method for preventing read disturbance accumulation in a cache memory. The method includes accessing a plurality of data lines in a cache set, generating a plurality of corrected data from a plurality of initial data based on a plurality of error correction codes (ECCs), and selecting a respective corrected data of the plurality of corrected data based on a respective way of a plurality of ways. Each of the plurality of data lines includes a respective data field of a plurality of data fields and a respective ECC field of a plurality of ECC fields. The plurality of initial data are stored in the plurality of data fields and the plurality of ECCs are stored in the plurality of ECC fields. Each of the plurality of ways is associated with a respective data line of the plurality of data lines.

Abstract: A circuit for reducing read disturbance error in a tag array. The circuit includes a decoder, a plurality of m-bit comparators, and a plurality of n-bit comparators. The decoder is configured to enable access to a respective set of the tag array based on a value of an index of a requested address. Each respective m-bit comparator is configured to enable access to a respective plurality of Most Significant Bits (MSBs) of the respective set responsive to each respective Least Significant Bit (LSB) of a respective plurality of LSBs of the respective set being equal to a respective LSB of a tag of the requested address. Each respective n-bit comparator is configured to enable access to the respective set by a data bus responsive to each respective MSB of the respective plurality of MSBs being equal to a respective MSB of the tag.

Abstract: A method for preventing read disturbance accumulation in a cache memory. The method includes accessing a plurality of data lines in a cache set, generating a plurality of corrected data from a plurality of initial data based on a plurality of error correction codes (ECCs), and selecting a respective corrected data of the plurality of corrected data based on a respective way of a plurality of ways. Each of the plurality of data lines includes a respective data field of a plurality of data fields and a respective ECC field of a plurality of ECC fields. The plurality of initial data are stored in the plurality of data fields and the plurality of ECCs are stored in the plurality of ECC fields. Each of the plurality of ways is associated with a respective data line of the plurality of data lines.

Abstract: A programmable logic unit (PLU). The PLU includes a plurality of four-input reconfigurable hard logics (RHLs), a three-input look-up-table (LUT), and a plurality of reconfigurable inverters. The plurality of RHLs include a first RHL, a second RHL, and a third RHL. The plurality of reconfigurable inverters are associated with the plurality of RHLs.