Abstract: A programmable logic unit (PLU). The PLU includes a plurality of four-input reconfigurable hard logics (RHLs), a three-input look-up-table (LUT), and a plurality of reconfigurable inverters. The plurality of RHLs include a first RHL, a second RHL, and a third RHL. The plurality of reconfigurable inverters are associated with the plurality of RHLs.
Type:
Grant
Filed:
February 13, 2018
Date of Patent:
June 4, 2019
Assignees:
HIGH PERFORMANCE DATA STORAGE AND PROCESSING CORPORATION, SHARIF UNIVERSITY OF TECHNOLOGY