Abstract: A Harvard-architecture computer simultaneously reads instructions using an instruction bus and accesses data over a separate data bus. A debug module has an external interface to an external debugger that initiates a debugging session by setting a debug bit in a debug mode register. When the debug bit is set, a first mux disconnects an instruction pointer and an instruction buffer from the instruction bus and instead connects the data bus to the instruction bus. A second mux disconnects a load/store unit in an execution core from the instruction bus and instead connects the debug module to the instruction bus. The external debugger sees a unified memory space and writes addresses to the debug module that are sent through the second mux to access the data memory, and instruction addresses are sent through the second mux and the first mux to the instruction memory to read or write instructions.

Abstract: An Integrated Circuit (IC) package has a ferrite-dielectric shield between a planar inductor coil and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in the inductor coil from reaching the semiconductor chip. The shield has a ferrite layer surrounded by upper and lower dielectric laminate layers to prevent electrical shorts. The center end of the inductor coil connects to the semiconductor chip through a center post that fits through an opening in the shield that is over the air core center of the inductor coil. The center post can connect to a die attach pad that the semiconductor chip is mounted to. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors. The outer end of the inductor coil connects to lead-frame outer risers also having external package connectors such as pins or bonding balls.

Abstract: A re-configurable bank of DC-DC converters has many channels, each with a DC-DC converter and a controller that senses the channel's output voltage and current to adjust a duty cycle of switch signals to the DC-DC converter. A serial bus connects to all controllers and writes digital voltage and current control targets into each controller. The controller has Digital-to-Analog Converters (DACs) that convert the targets to analog voltages that are compared to sensed output voltage and current. The comparison results are compared to a sawtooth wave to generate pulses of the switch signals that have a duty cycle adjusted for the target comparisons. In combined mode, a primary channel's controller generates switch signals for secondary channels having outputs shorted to the primary channel. Secondary channels have a mux to select switch signals from the primary controller during combined mode, and from the secondary controller during separated mode.

Abstract: A modulator spreads the spectrum of a generated clock to reduce Electro-Magnetic Interference (EMI). A capacitor is charged by a variable current to generate a ramp voltage that is compared to a reference to end a clock cycle and discharge the capacitor. An up-down counter drives a Digital-to-Analog Converter (DAC) that controls the variable charging current to provide triangle modulation. A smaller offset current is added or subtracted for cubic modulation when the up-down counter reaches its minimum count. A frequency divider that clocks the up-down counter also clocks a Linear-Feedback Shift-Register (LFSR) to that controls pseudo-random current sources that further modulate variable current and frequency. The LFSR is clocked with the up-down counter to modulate each frequency step, or only at the minimum count to randomly modulate at the minimum frequency. Binary-weighted bits from the up-down counter to the DAC are swapped to modulate the frequency step size.