Abstract: A hot swap circuit board and associated cable and connector arrangement for an ATA100 computer-disk drive interface is disclosed. The hot swap circuit board comprises a key-switched power supply control circuit with a simultaneously key-operated mechanical lock, a logic control circuit for READ and WRITE control signals and a set of logic switchable bi-directional impedance circuits with signal regeneration for the control and data signals across the ATA100 Interface. During normal operation, a security lock on the hot swap circuit board is kept in its locked position thus preventing any accidental disconnection of the ATA100 interface connector while simultaneously supplying electrical power and transmitted and regenerated control and data signals across the ATA100 interface. The unlocking mechanism is also disclosed.

Abstract: An improved ECL circuit, based upon an ECL circuit of conventional design, functions as the required transceiver for the bi-directional data transmission between a computer and an electronic device with a specific interface of USB 2.0. The value of an emitter resistor within an emitter resistance network in the conventional ECL circuit is adjusted till its output voltage amplitude meets the USB 2.0 specification. A number of voltage level shifting and capacitive coupling circuits are added to both the input and output sections of the conventional ECL circuit making it directly interfaceable with the popular CMOS logic family. A collector electrode switch network is also added to the conventional ECL circuit to make its output terminals tri-statable thus compatible with the communication scheme of half duplexing under the USB 2.0 specification.

Abstract: An improved ECL circuit, based upon an ECL circuit of conventional design, functions as the required transceiver for the bi-directional data transmission between a computer and an electronic device with a specific interface of USB 2.0. The value of an emitter resistor within an emitter resistance network in the conventional ECL circuit is adjusted till its output voltage amplitude meets the USB 2.0 specification. A number of voltage level shifting and capacitive coupling circuits are added to both the input and output sections of the conventional ECL circuit making it directly interfaceable with the popular CMOS logic family. A collector electrode switch network is also added to the conventional ECL circuit to make its output terminals tri-statable thus compatible with the communication scheme of half duplexing under the USB 2.0 specification.