Patents Assigned to Hiji High-Tech Co., Ltd.
  • Patent number: 7973571
    Abstract: The invention provides a multichannel drive circuit by which, even when there occurs a variation between channels in circuit characteristics of each channel including current source due to the semiconductor manufacturing process and the like, loads of each channel constituting a load array can be driven under conditions uniform between all the channels. The invention includes; an interchannel common connection line (5) for making conduction between respective current paths of each channel for connecting the respective current sources of each channel constituting a current source array (11) with respective input switches of each channel constituting an input switch array (13); and current blocking means (12) for blocking output current of the current source of that channel of the plurality of channels in which the input switch is in an OFF state from flowing into the interchannel common connection line.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: July 5, 2011
    Assignee: Hiji High-Tech Co., Ltd.
    Inventors: Tatsumi Sato, Kazuhiko Maki, Toshiyuki Wada, Takamasa Yanai
  • Patent number: 7746126
    Abstract: To provide a load drive circuit that has a satisfactory phase characteristic and can be realized as a low-price LSI chip. A series circuit of nonlinear resistive elements (P2 and N3) and switch elements (N2 and P3) is inserted between control input terminals (GP1 and GN1) of output elements (P1 and N1) of a final amplifier (AMP0) and an output terminal (OUT) of the load drive circuit. The nonlinear resistive element has a nonlinear characteristic in which a resistance value decreases as an applied voltage value increases and the resistance value increases as the applied voltage value decreases. The switch elements are switching-controlled to selectively come into an ON state only in a high-electric potential period or a low-electric potential period of an input signal according to whether the output element is arranged on a high-electric potential side or a low-electric potential side in the final amplifier.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: June 29, 2010
    Assignee: Hiji High-Tech Co., Ltd.
    Inventor: Takeda Koji
  • Publication number: 20090302898
    Abstract: The invention provides a multichannel drive circuit by which, even when there occurs a variation between channels in circuit characteristics of each channel including current source due to the semiconductor manufacturing process and the like, loads of each channel constituting a load array can be driven under conditions uniform between all the channels. The invention includes; an interchannel common connection line (5) for making conduction between respective current paths of each channel for connecting the respective current sources of each channel constituting a current source array (11) with respective input switches of each channel constituting an input switch array (13); and current blocking means (12) for blocking output current of the current source of that channel of the plurality of channels in which the input switch is in an OFF state from flowing into the interchannel common connection line.
    Type: Application
    Filed: November 20, 2006
    Publication date: December 10, 2009
    Applicant: Hiji High-Tech Co., Ltd.
    Inventors: Tatsumi Sato, Kazuhiko Maki, Toshiyuki Wada, Takamasa Yanai
  • Patent number: 5675278
    Abstract: An output circuit of a level shifter or an operational amplifier which converts input signal voltages to different voltage levels. A pMOS transistor PT.sub.2 and nMOS transistor NT.sub.2 connected in series between the power source and ground constitute the output node ND.sub.12. A Wilson mirror is made of pMOS transistors PT.sub.3 -PT.sub.6. An nMOS transistor NT.sub.3 induces a current flow in the current mirror, and an nMOS transistor NT.sub.1 connected between the current output node ND.sub.1 of the current mirror and ground. The gate of pMOS transistor PT.sub.2 is connected to the current output node ND.sub.1, and the gates of nMOS transistor NT.sub.1 and nMOS transistors NT.sub.2 and NT.sub.3 are connected to the input line of signals IN and XIN, which are 180.degree. out of phases.
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: October 7, 1997
    Assignee: Texas Instruments Incorporated/Hiji High-Tech Co., Ltd.
    Inventors: Shinichi Tanaka, Takehiro Takayanagi, Yasuhisa Uchida