Abstract: A switch device for source drivers of liquid crystal displays includes a first switch module; a first switch; a second switch; a second switch module; a third switch module; a fourth switch module; a third switch; and a fourth switch; wherein when a first driving signal with a voltage level between a first voltage level and a second voltage level through the second switch module is sent to a second output terminal and a second driving signal with a voltage level between a third voltage level and a fourth voltage level through the third switch module is sent to a first output terminal, the first switch is turned on such that a first node is connected to a first voltage source with the first voltage level and the fourth switch is turned on such that a second node is connected to a fourth voltage source with the fourth voltage level.

Abstract: A level shifter for a source driver of a liquid crystal display is provided. The level shifter includes: an input stage for generating a signal with a voltage of between a positive input source voltage and a negative input source voltage according to an input logic; a middle stage for generating a first logic signal and a second logic signal according to the signal; and an output stage, for generating a first output signal with a voltage of between a first positive output source voltage and a first negative output source voltage at a first output terminal or a second output signal with a voltage of between a second positive output source voltage and a second negative output source voltage at a second output terminal according to the first logic signal and the second logic signal.

Abstract: An image display system and a pixel array driving method thereof. The image display system has a source driver having a first and a second digital-to-analog converter and a first and a second switching circuit. The first digital-to-analog converter converts an N-bit digital code to a first analog signal, where N is a positive integer. The second digital-to-analog converter converts a K-bit digital code to a second analog signal, where K is a positive integer and is smaller than N. The first switching circuit controls coupling between a first display data, a second display data and the first and second digital-to-analog converters, and, the second switching circuit controls connections between the first and second analog signals and a first and a second operational amplifier. The first and second operational amplifiers are coupled to a first and a second data line of a pixel array, respectively.

Abstract: A luminance compensation apparatus for an OLED panel including a luminance integration unit and a luminance compensation unit is provided. The luminance integration unit is used for respectively integrating a luminance value for each dot of an OLED panel before a current frame period to obtain an integrated luminance value for each dot of the OLED panel. The luminance compensation unit is used for respectively converting the integrated luminance value for each dot of the OLED panel to a compensation luminance value for each dot of the OLED panel according to a compensation lookup table, and generating an output luminance value for each dot of the OLED panel according to the compensation for luminance value for each dot of the OLED panel and a luminance value for each dot of the OLED panel at the current frame period to drive signals to compensate luminance for each dot of the OLED panel.

Abstract: The invention discloses an impedance design method for a power network of a core chip within a chipset having N input/output (I/O) ports coupled to a voltage source which have an observation I/O port. The method includes calculating a first set of impedances at a predetermined frequency or the observation I/O port, if the voltage source is internally coupled to the N I/O ports within the chipset, and calculating a second set of impedances at the predetermined frequency for the observation I/O port, if the voltage source is externally coupled to the N I/O ports through a carrier coupling the core chip to the voltage source. The first set of impedances to the second set of impedances are compared, and the impedance of the power network or the impedance of the carrier is adjusted according to the comparison result.

Abstract: During transition, level shifters in a source driver output logic high signals to PMOS DACs and output logic low signals to NMOS DACs for shutting down current paths in the PMOS DACs and in the NMOS DACs. Therefore, during transition, the PMOS DACs and the NMOS DACs are at high-impedance stage for preventing gamma coupling effect.