Patents Assigned to HIPER SEMICONDUCTOR INC.
  • Patent number: 12677463
    Abstract: A high electron mobility transistor (HEMT) includes a GaN epi-layer, a first passivation layer, a source electrode metal, a drain electrode metal, a gate electrode metal, and a field plate. The first passivation layer is deposited on the GaN epi-layer. The source electrode metal, the drain electrode metal, and the gate electrode are recessed into the first passivation layer and deposited on the GaN epi-layer. The source electrode metal has a source field plate with a source field plate length Lsf. The drain electrode metal has a drain field plate with a drain field plate length Ldf, wherein Ldf>Lsf. The gate electrode is situated between the source electrode metal and the drain electrode metal. The field plate is situated between the gate electrode and the drain electrode metal.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: July 7, 2026
    Assignee: HIPER SEMICONDUCTOR INC.
    Inventors: Yan Lai, Wei-Chen Yang
  • Patent number: 12543363
    Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: February 3, 2026
    Assignee: HIPER SEMICONDUCTOR INC.
    Inventors: Yan Lai, Wei-Chen Yang
  • Publication number: 20250185273
    Abstract: A high electron mobility transistor includes a semiconductor structure, a stepped trench, an electrode, and a gate. The semiconductor structure includes a barrier layer and a channel layer. The barrier layer is disposed on the channel layer. A two-dimensional electron gas is formed at an interface between the channel layer and the barrier layer. The stepped trench is disposed in the semiconductor structure. The electrode is disposed in the stepped trench. The gate is disposed on the barrier layer. The stepped trench has a first width and a second width. The first width is greater than the second width.
    Type: Application
    Filed: November 5, 2024
    Publication date: June 5, 2025
    Applicant: HiPer Semiconductor Inc.
    Inventors: WEI-CHEN YANG, WEI-CHIH HO
  • Publication number: 20250185272
    Abstract: A semiconductor structure of a high electron mobility transistor includes a channel layer, a barrier layer, a gate, a n-type material structure, and a metal electrode. The barrier layer is formed on the channel layer. A two-dimensional electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer. The gate is formed on the barrier layer. The n-type material structure is in contact with the barrier layer. The metal electrode is a drain or a source and is disposed on a side of the gate.
    Type: Application
    Filed: November 5, 2024
    Publication date: June 5, 2025
    Applicant: HiPer Semiconductor Inc.
    Inventors: WEI-CHEN YANG, WEI-CHIH HO
  • Publication number: 20250169125
    Abstract: A high electron mobility transistor includes a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The buffer layer includes a first buffer region, a second buffer region and a third buffer region. The first buffer region includes a first III-nitride stacked layer disposed on the nucleation layer and a second III-nitride stacked layer disposed on the first III-nitride stacked layer. The second buffer region is doped with carbon and iron. The third buffer region is doped with carbon and iron and has a carbon concentration greater than an iron concentration of the third buffer region. The second III-nitride stacked layer is doped with carbon and iron and has a carbon concentration greater than an iron concentration of the second III-nitride stacked layer.
    Type: Application
    Filed: October 22, 2024
    Publication date: May 22, 2025
    Applicant: HiPer Semiconductor Inc.
    Inventors: PO-JUNG LIN, WEI-CHEN YANG
  • Patent number: 11848376
    Abstract: A high electron mobility transistor (HEMT) includes a GaN epi-layer, a first passivation layer, a source electrode metal, a drain electrode metal, a gate electrode metal, and a field plate. The first passivation layer is deposited on the GaN epi-layer. The source electrode metal, the drain electrode metal, and the gate electrode are recessed into the first passivation layer and deposited on the GaN epi-layer. The source electrode metal has a source field plate with a source field plate length Lsf. The drain electrode metal has a drain field plate with a drain field plate length Ldf, wherein Ldf>Lsf. The gate electrode is situated between the source electrode metal and the drain electrode metal. The field plate is situated between the gate electrode and the drain electrode metal.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: December 19, 2023
    Assignee: HIPER SEMICONDUCTOR INC.
    Inventors: Yan Lai, Wei-Chen Yang
  • Patent number: 11799000
    Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: October 24, 2023
    Assignee: HIPER SEMICONDUCTOR INC.
    Inventors: Yan Lai, Wei-Chen Yang