Patents Assigned to Hiroshi Nakamura
  • Patent number: 5438669
    Abstract: A plurality of physical registers greater in number than can be addressed by instructions are provided. The physical registers are divided into a plurality of partial groups or windows. Each of the physical registers is specified by a physical register number determined by a combination of the number of the window and a register number contained in the window. The window number is indicated by a current floating point window pointer stored in a current floating point window pointer register. In executing a vector calculation program having repetitive loops of an instruction sequence, the window is changed for each loop by changing the value of the current floating point window pointer. Vector data to be calculated at the i-th loop is read from a main memory at the loop before the i-th loop.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: August 1, 1995
    Assignees: Hitachi, Ltd., Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori
    Inventors: Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Hideo Wada