Patents Assigned to Hitachi Advanced Digital, Inc.
  • Patent number: 7386064
    Abstract: In one embodiment, a PLL circuit is provided with a plurality of pull-in operation modes for pulling a voltage across a filter capacitor (C1, C2) in a lock-up voltage, and with a register (CRG) for designating one of the plurality of pull-in operation modes. The pull-in operation is performed in accordance with a setting value in the register.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: June 10, 2008
    Assignees: Renesas Technology Corp., TTPCOM Limited, Hitachi Advanced Digital, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Koichi Yahagi, Ryoji Furuya, Fumiaki Matsuzaki, Robert Astle Henshaw
  • Patent number: D718360
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 25, 2014
    Assignee: Hitachi Advanced Digital, Inc.
    Inventors: Kosuke Matoba, Atsushi Ishibashi, Toshiyuki Moriya, Takashi Yamamoto, Shinichi Ishikuro