Abstract: Methods and apparatus directed to reducing blockiness resulting from encoding digital video data using, e.g., DCTs are disclosed. An encoder which encodes video signals into a digital video bitstream including information identifying blocky video and instructions for processing the blocky video is also disclosed. A plurality of methods of identifying blocky video in an encoded bitstream by analyzing the encoded bitstream are also disclosed. In addition, various methods of filtering both non-blocky and blocky video, without adversely affecting the non-blocky video, are described.

Abstract: A Nyquist filter implemented as a FIR filter comprising a series of N filter cells, where N is an integer is disclosed. The Nyquist filter is especially well suited for use in demodulators capable of demodulating both VSB and QAM signals. During VSB mode operation, each filter cell acts as a single tap of an N tap Nyquist filter. During QAM mode operation, an additional unit delay element, not used during VSB mode operation, is inserted into the signal path of each cell of the Nyquist filter. The introduction of this second unit delay element into the signal path of each filter cell effectively serves to convert each filter cell into two filter taps with the coefficient of the second filter tap being zero. Thus, during QAM mode operation, the Nyquist filter of the present invention operates as a 2N-tap FIR filter which has coefficients of zero for half of the 2N taps.

Abstract: A video decoder capable of downsampling full resolution images on a block by block basis regardless of the downsampling rate is disclosed. When the applied downsampling rate does not divide evenly into the number of pixel values included in a block in the dimension being downsampled, the decoder generates a partial pixel value. A partial pixel value represents a portion of the information used to represent a pixel of an image. In contrast, a full or complete pixel value is a value represents all the information used to represent a pixel of an image. The generated partial pixel value is stored and then added to another partial pixel value generated by downsampling another block of pixel values corresponding to a portion of a full resolution image. Numerous drift reduction processing techniques applicable to downsampling decoders are disclosed. Many of these processing techniques are applicable to decoders which perform full order IDCTs as well as reduced order IDCTs.

Abstract: Methods and apparatus for providing implementation efficient adaptive equalizers suitable for use with QAM and/or VSB signals are disclosed. Finite impulse response ("FIR") filters are used to implement the disclosed adaptive equalizers. A plurality of arithmetic operator sharing techniques are disclosed for reducing the number of arithmetic operators required to implement the adaptive equalizers. In addition, methods of reconfiguring the arithmetic operators used to implement a QAM equalizer so that they can be used to implement a VSB equalizer circuit are disclosed. Methods of the present invention use multiplexers to reconfigure the FIR filters from a complex decimating FIR filter for use during QAM operation, to a half complex feedforward FIR filter and a real decision feedback FIR filter suitable for use during VSB mode operation of the equalizer circuit of the present invention.

Abstract: An apparatus and method for providing short circuit current free dynamic logic building blocks comprising P-logic and N-logic dynamic domino building blocks having separate clocks for driving the P-logic and N-logic evaluate and pre-charge stages. The P-logic building gates are pre-charged to a zero volt output and upon the transition from high to low on the input line, will provide a high output during the evaluation cycle. Conversely, the N-logic building blocks are pre-charged with a high output level and upon the transition of a low to high input to the building block device, will provide a low output signal during the evaluation period. Both building block types are pre-charged again at the end of the evaluation period to provide an inherently glitch-free dynamic logic device. Separate evaluate and charge clock signals are provided to each of the P-logic and N-logic building blocks which are configured to provide a non-overlapping charge and evaluation cycle.

Abstract: A digital signal processor that includes an instruction memory, a program control unit, and an instruction decoder. The instruction memory stores a sequence of instruction words including DSP instruction words and RISC instruction words. The program control unit outputs an instruction address to the instruction memory so as to select one instruction word in the instruction memory. Every DSP instruction word identifies one data processing operation and one data transfer operation to be performed. The DSP instruction words include a predefined DSP instruction word having separate source and destination fields for specifying register locations for data sources and data destinations. The RISC instruction words include a predefined RISC instruction word corresponding to the predefined DSP instruction word. The predefined RISC instruction word has separate source and destination fields for specifying register locations for data sources and data destinations.

Abstract: Methods and apparatus for automaticly distinguishing between QAM and VSB modulated signals and, for implementing an automatic VSB/QAM modulation recognition circuit are described. In accordance with various described embodiments, a narrow digital passband filter is used to sweep across the frequency region of a received HDTV signal where a VSB pilot tone would be located if the received signal is a VSB signal. The power of the filtered HDTV signal is estimated and compared to various preselected thresholds. If a power threshold value indicative of the presence of a VSB pilot tone is exceeded VSB is declared present. If no VSB pilot tone is detected, as indicated by the measured signal power levels, receipt of a QAM signal is declared. Various methods of insuring that transient changes in a received signal do not result in an erroneous decision with regard to the type of demodulation to perform are also described.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: A digital video tape recorder ("VTR") that selects data useful for generating images during trick playback operation and records the data in trick play tape segments arranged on a tape to form fast scan tracks and multi-speed playback tracks. Each fast scan track comprises trick play tape segments located on a diagonal, relative to the length of the tape, of the same angle as the angle at which the heads of a VTR are expected to pass over the tape during trick play operation at a specific speed and direction of operation. Each multi-speed playback track comprises a plurality of trick play tape segments arranged parallel to the length of the tape. Data which is used for at least one mode of trick play operation is recorded in each trick play tape segment. Each fast scan track and multi-speed track crosses multiple normal play tracks.

Abstract: A procedure for selecting and storing data elements communicated from a common database to users of the database utilizing a communication link between each transmitter and a concomitant receiver accessible by the user. The transmitted information is augmented with attributes which are used at the receiver to select and then store locally only that information of interest to each receiver's user, wherein the attributes and the user selection pattern determine the criteria for storing information locally. Attributes include: utility of each data element in time; interest categories and level of interest for each of the categories determined for the collective users; repeat time to the data element; and a hyperlink to associated data elements.

Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Methods and apparatus for reducing the complexity of decoder circuitry and video decoder memory requirements are disclosed. The described video decoders are capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: A cold start fuel control system provided for use with an internal combustion engine of the type having at least one combustion chamber, an air/fuel passageway fluidly connected with the combustion chamber and the source of fuel. The fuel control system includes an annular heater having an interior annular wall disposed within the passageway. A cold start fuel injector has its inlet fluidly connected to the fuel source and an outlet open to the passageway such that fuel from the outlet flows into the interior of the heater. Whenever the operating temperature of the engine is below a predetermined level, fuel is selectively provided to the cold start fuel injector which injects fuel into the passageway. The fuel discharge from the cold start fuel injector is swirled so that at least a portion of the fuel from the cold start fuel injector impinges upon the annular heater and is thus vaporized.

Abstract: An integrated premixture chamber is disclosed, for mixing gaseous fuel and air for delivery to a combustion chamber of an internal combustion engine. The integrated premixture chamber includes a mass air flow sensor, a throttle valve and position sensor, a fuel shut-off valve, a gas flow sensor and a fuel metering valve having discharge outlets downstream of the mass air flow sensor to provide more accurate metering. The integrated premixture chamber is controlled by an electronic unit separate from the engine's control unit.

Abstract: Methods and apparatus for processing digital video data to reduce the amount of video data required to represent a video frame by representing a frame or pair of field pictures into a single field of a pair of field picture are described. To prevent the second field of the field picture from being displayed a DSM byte associated with the field picture is set so that only the field representing the video frame is displayed. In accordance with the present invention, a field, e.g., a transparent predictively coded field is used as the field picture which is not displayed. In this manner, very little data is required to represent the field picture that is not displayed. When the received frames are represented as pairs of field pictures a single field of the pair of field pictures is selected to represent the video frame with the other field picture being replaced with a field which requires very little data.

Abstract: Methods of operating a digital video recording and playback device, such as a video tape recorder, to arrange trick play data into one or more groups, to generate error correction bits for each group of trick play data, e.g., a group of trick play data blocks, and to correct the data after being read back using the error correction bits is disclosed. The trick play data blocks are made to be smaller than normal play data blocks with multiple trick play data blocks being equal in size to a single normal play data block. By making a group of trick play data blocks equal in size to a single normal play data block, the group of trick play data blocks may be processed as a unit by the same error correction circuitry and in the same manner used to process individual normal play data blocks. In accordance with one embodiment, the error correction bits for a group of trick play data blocks are calculated treating the data in the group of trick play data blocks as a single unit.

Abstract: An architecture for a memory with a wide word, e.g. n-byte, width particularly suited for use as a high definition video frame store memory (80), and an accompanying organization for storing pixel data therein to facilitate efficient block and raster access therefrom. Specifically, the memory relies on storing n-byte wide words (n=(m.sub.1 .times.m.sub.2)) across m.sub.2 independent m.sub.1 -byte wide memory segments, with pre-defined positional offsets between respective m.sub.1 -byte words (203)("nibbles") stored in successive memory segments. All these segments are simultaneously accessed on a read or write basis. During a memory write operation, all the nibbles in an n-byte wide input word are appropriately shuffled to yield the proper inter-segment offsets prior to being written into the memory as a collective n-byte memory write word. During a read operation, all the nibbles read from memory in a collective n-byte memory read word are appropriately shuffled to yield an n-byte output word.

Abstract: Digital video tape recorder apparatus that generates commands to instruct a television receiver to perform special processing, e.g., processing designed to enhance image quality, on video data received from the digital video tape recorder during trick play operation is disclosed. The commands from the video tape recorder inform the television receiver that the video tape recorder is operating in trick play mode and that video processing not performed on normal play video data output by the video tape recorder during normal play operation should be performed on the trick play video data which is output during trick play operation. The video data output during trick play operation is a subset of the normal play video data. The video processing commands output during trick play operation instruct a receiver to perform video processing intended to compensate for normal play data intentionally omitted by the video tape recorder from the trick play video data because of, e.g.

Abstract: A method and apparatus for controlling the display of progressively refreshed decoded compressed image representative data is disclosed. Subframes of intracoded video signals, and subframes of intercoded video signals based on the intracoded video signals of successive video frames are used to construct a reference video frame. Refresh descriptor data is provided indicating the number of video frames necessary for acquiring intracoded video signals to form the reference video frame. The display of video frames is inhibited based on the refresh descriptor data until a suitable video frame of intracoded video signals and intercoded video signals based thereon is constructed. In another embodiment of the invention, at least one array of memory elements is provided for storing data corresponding to the subframes of a video frame. Each subframe of a video frame corresponds to one element of the memory array.

Abstract: An apparatus and method for varying the slew rate of a digital AGC circuit is disclosed. A gain amplifier receiving an analog signal from a tuner is converted by an A/D converter into a digital form. An ABS circuit then obtains an absolute value level of the signal, which is then low pass filtered. The filtered signal is compared to a reference level to determine if the gain should be increased or decreased. The filtered signal is also communicated to a lock detect circuit to determine how far out of the desired range the signal is, thereby requiring large step changes for a fast, coarse adjustment or smaller step changes fine adjustment of the gain. An integrator combines the two results to determine the varying slew rate of the gain signal, which is converted back to the analog domain to control the amplifier.