Abstract: A multistage high frequency power amplifier-circuit device has a plurality of semiconductor amplification elements connected in a cascade. The circuit device is provided with a bias control circuit used to control the bias voltage or bias current of the output semiconductor amplification element in each stage so as to reduce the variation of the output power with respect to the power control signal voltage in an area around the threshold voltage of the semiconductor amplification elements. This realizes a high frequency power amplifier circuit device provided with excellent controllability of the output power and high efficiency at the time of low power output realized with use of such a control voltage as a power control signal.

Abstract: A module including a bias circuit that generates gate bias voltages by resistance dividers creates a problem in that the values of the resistances constituting the bias circuit must be finely adjusted, and accordingly extra trimming tasks are required. The present invention provides current generators that generate currents varying with desired characteristics responsive to a control voltage, independent of variations in transistor threshold voltages, connects output resistors to parallel transistors in respective stages to form current mirror circuits, and supplies currents from the current generators thereto to drive them, instead of supplying dividing voltages.

Abstract: A multistage high frequency power amplifier circuit device has a plurality of semiconductor amplification elements connected in a cascade. The circuit device is provided with a bias control circuit used to control the bias voltage or bias current of the output semiconductor amplification element in each stage so as to reduce the variation of the output power with respect to the power control signal voltage in an area around the threshold voltage of the semiconductor amplification elements. This realizes a high frequency power amplifier circuit device provided with excellent controllability of the output power and high efficiency at the time of low power output realized with use of such a control voltage as a power control signal.

Abstract: The required RAM capacity is reduced by dividing an interleaving RAM in a baseband modulator into a plurality of areas and having the read side and the write side use some common areas on a time-sharing basis.

Abstract: A module including a bias circuit that generates gate bias voltages by resistance dividers creates a problem in that the values of the resistances constituting the bias circuit must be finely adjusted, and accordingly extra trimming tasks are required. The present invention provides current generators that generate currents varying with desired characteristics responsive to a control voltage, independent of variations in transistor threshold voltages, connects output resistors to parallel transistors in respective stages to form current mirror circuits, and supplies currents from the current generators thereto to drive them, instead of supplying dividing voltages.

Abstract: A switching system for realizing integration of existing communication networks or interconnections thereof, and a switching control method. After a call is originated from an ATM communication network 101 to an STM communication network 102, an ATMIF 20 that has received a connection request signal (control signal) converts the control signal into a format of an ATM cell 1000, adds a header destined to one of SIG 50-1 to n for processing control signals, and then output the same. An ATMSW 10 performs self-routing based on header information. The selected one of the SIG 50-1 to n performs conversion for the ATM cell 1000 by a specified protocol, makes an ATM cell 1100 having a header destined to one of CLP 630-1 to k for processing control signals, and then output the same. Upon having received the ATM cell 1100, the CLP 630 links up with other processors to perform call connection control, functions having been dispersed among the other processors.

Abstract: A multistage high frequency power amplifier-circuit device has a plurality of semiconductor amplification elements connected in a cascade. The circuit device is provided with a bias control circuit used to control the bias voltage or bias current of the output semiconductor amplification element in each stage so as to reduce the variation of the output power with respect to the power control signal voltage in an area around the threshold voltage of the semiconductor amplification elements. This realizes a high frequency power amplifier circuit device provided with excellent controllability of the output power and high efficiency at the time of low power output realized with use of such a control voltage as a power control signal.

Abstract: A module including a bias circuit that generates gate bias voltages by resistance dividers creates a problem in that the values of the resistances constituting the bias circuit must be finely adjusted, and accordingly extra trimming tasks are required. The present invention provides current generators that generate currents varying with desired characteristics responsive to a control voltage, independent of variations in transistor threshold voltages, connects output resistors to parallel transistors in respective stages to form current mirror circuits, and supplies currents from the current generators thereto to drive them, instead of supplying dividing voltages.

Abstract: A multistage high frequency power amplifier circuit device has a plurality of semiconductor amplification elements connected in a cascade. The circuit device is provided with a bias control circuit used to control the bias voltage or bias current of the output semiconductor amplification element in each stage so as to reduce the variation of the output power with respect to the power control signal voltage in an area around the threshold voltage of the semiconductor amplification elements. This realizes a high frequency power amplifier circuit device provided with excellent controllability of the output power and high efficiency at the time of low power output realized with use of such a control voltage as a power control signal.

Abstract: A module including a bias circuit that generates gate bias voltages by resistance dividers creates a problem in that the values of the resistances constituting the bias circuit must be finely adjusted, and accordingly extra trimming tasks are required. The present invention provides current generators that generate currents varying with desired characteristics responsive to a control voltage, independent of variations in transistor threshold voltages, connects output resistors to parallel transistors in respective stages to form current mirror circuits, and supplies currents from the current generators thereto to drive them, instead of supplying dividing voltages.

Abstract: Disclosed is a telephone circuit in which two simultaneously available telephones are connected by use of a pair of twisted-paired cables. A PBX 1 and a digital multi-function telephone 2 are connected by a pair of twisted-paired cables, a digital signal channel of 2B+D is established bidirectionally between the PBX 1 and the digital multi-function telephone 2, and user information and a control signal are sent and received therebetween. The digital multi-function telephone 2 and an analog telephone 3 are connected by a pair of twisted-paired cables, and a signal is sent and received between the digital multi-function telephone 2 and an analog telephone 3 by an analog signal of a voice band and a DC/AC control signal. A B1-channel on a 2-wire digital line 4 is allocated for user information transmission of the digital multi-function telephone 2, and a B2-channel is allocated for user information transmission of the analog telephone 3.

Abstract: A wireless communication apparatus, which is designed to control the output power without using the power control signal sent from the base station, comprises a high-frequency power amplifier for transmission, a detection means which measures the output power of the power amplifier, and an automatic power control circuit which controls the output power of the power amplifier based on information provided by the detection means. The power amplifier includes an amplifying system which has multiple amplifying stages and is connected between the input and output terminals, and bias circuits which supply bias voltages to transistors of the respective amplifying stages. The bias circuits, which supply the bias voltages to the multiple amplifying stages excluding the last amplifying stage, are each made up of multiple resistors.

Abstract: A temperature compensating circuit includes a first circuit network 1 between an inverting input terminal of an operational amplifier 13 and an output terminal of the operational amplifier 13, and a second circuit network 2 between the inverting input terminal of the operational amplifier 13 and a reference potential. At least one of the first circuit network and the second circuit network is made of an arrangement containing a plurality of series-connected thermistor/resistor pairs in which the thermistors are connected parallel to the resistors, and the temperature compensating circuit compensates a temperature-dependent signal which is inputted into a positive phase input terminal of the operational amplifier 13, and outputs the temperature-compensated signal.

Abstract: An optical transmitter for use in an optical transmitting system based on PDS (Passive Double Star) technology, does not erroneously output an optical signal when the optical transmitter is powered on/off. The optical transmitter has a current source 1 for outputting a drive current having a magnitude corresponding to an input control signal, a Laser diode (LD) for generating an optical output signal based on the received drive current, a modulator 9 for controlling the supply and cutoff of the drive current to the Laser diode (LD), a source voltage detector 3 for monitoring a source voltage to detect whether the source voltage is lower than a predetermined voltage, and a switch circuit 4 for outputting a control signal to the current source 1 to stop the supply of the drive current when the source voltage is determined to be lower than the predetermined voltage.

Abstract: A temperature compensating circuit includes a first circuit network 1 between an inverting input terminal of an operational amplifier 13 and an output terminal of the operational amplifier 13, and a second circuit network 2 between the inverting input terminal of the operational amplifier 13 and a reference potential. At least one of the first circuit network and the second circuit network is made of an arrangement containing a plurality of series-connected thermistor/resistor pairs in which the thermistors are connected parallel to the resistors, and the temperature compensating circuit compensates a temperature-dependent signal which is inputted into a positive phase input terminal of the operational amplifier 13, and outputs the temperature-compensated signal.

Abstract: A cell/packet assembly and disassembly apparatus is provided for efficiently connecting a line in a line switching system to an ATM network or a packet network, without causing congestion, to transmit and receive cells or packets therebetween. The cell/packet assembly and disassembly apparatus, upon detecting a call setting request outputted from a line switch board in response to a call originated from a terminal, starts cell assembly and cell disassembly of user information transmitted and received between a channel on a line in the line switching system corresponding to the call setting request and a virtual channel on the ATM network assigned to the channel.

Abstract: A signal receiving circuit comprising a first P-channel MOSFET amplifier and a first N-channel MOSFET amplifier having gates supplied with positive signals from a pair of signal transmission lines; and a second P-channel MOSFET amplifier and a second N-channel MOSFET amplifier having gates supplied with negative signals from said pair of signal transmission lines; wherein a first output signal is formed by so adjusting the gains of the first P-channel MOSFET amplifier and of the second N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages, and a second output signal is formed by so adjusting the gains of the second P-channel MOSFET amplifier and of the first N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages.

Abstract: In an incoming call service by which an extension can be directly called when a call comes in from another office, a dedicated terminal for selecting an extension to which the incoming call is connected is installed to enable the user to select it as desired, thereby increasing usage of call incoming lines for effective use. An exchange which connects an incoming call from another office directly to an extension, an input device for accepting specification of an extension corresponding to a specific incoming call, and a controller which includes a definition device for defining the correspondence between the specific incoming call and extension are provided. Upon receipt of an incoming call, the exchange connects the call to its corresponding extension in response to the correspondence defined in the definition device.

Abstract: A cell/packet assembly and disassembly apparatus is provided for efficiently connecting a line in a line switching system to an ATM network or a packet network, without causing congestion, to transmit and receive cells or packets therebetween. The cell/packet assembly and disassembly apparatus, upon detecting a call setting request outputted from a line switch board in response to a call originated from a terminal, starts cell assembly and cell disassembly of user information transmitted and received between a channel on a line in the line switching system corresponding to the call setting request and a virtual channel on the ATM network assigned to the channel.

Abstract: A bus type clock supplying system in a communication system with master-slave synchronization includes communication cards connected with transmission lines within a communication system and a clock bus. Each communication card includes a clock supplying section including a frequency divider for extracting a clock from the transmission lines and a tri-state device outputting the clock to the clock bus; a clock receiving section including a clock selector for selecting one clock from a plurality of the bus-type clock lines, and a frequency multiplier for multiplying the frequency of the selected clock; and a monitoring and controlling section having a function of monitoring interruption of clock input, abnormalities in the frequency multiplier, etc., and a function of controlling the tri-state device and the clock selector.