Abstract: A design support system for executing logic verification so as to perform work management, progress state management and logic quality management efficiently in a logic verification process and so as to improve the man-hour for development and the throughput of computer resources. For every verification item to be executed, management information including a verification item number for identifying a verification item, confirmation information for indicating the fact that no failure has been confirmed in the verification item, a prerequisite verification item number for identifying another verification item required to be confirmed as a prerequisite for the verification item is stored in a memory of the system.

Abstract: An information processing system includes a central processing unit, a main storage, a main storage controller for controlling the main storage, a cache memory having a content of at least one part of addresses stored in the main storage, at least one DMA controller which is capable of referring to the main storage and a DMA address translation unit for translating a logical address outputted from the DMA controller into a physical address for referring to the main storage. The DMA address translation unit has a flag representing whether or not the cache memory is referred to on DMA. The main storage controller performs either of reference to the cache memory or direct reference to the main storage based upon the flag on DMA.

Abstract: Memory expansion using memory packages of different generations is performed without unnecessarily increasing the minimum memory capacity of a memory device and while obtaining a high error detecting ability and high reliability. In expanding the capacity of a memory device by using first generation 1M.times.1 bit IC memory packages, second generation 4M.times.4 bits IC memory packages, or third generation 16M.times.8 bits IC memory packages, the total code length is set to 40 bits, a 4's multiple, within a range longer than the total code length necessary for S4ED and shorter than the total code length necessary for S8ED, and a reduced code is used for enhancing the S8ED function. In this manner, wasteful first generation IC memory packages can be reduced in number, and the error detecting ability of a memory device using third generation memory packages can be retained substantially the same as that of a memory device using first generation memory packages.

Abstract: The present invention relates to an integrated circuit comprising a semiconductor chip having thereon a logical function portion for realizing logical function and at least one power supply point for supplying electric power to the logical function portion, and at least one first, second and third power trunk line are arranged on the chip for supplying electric power from the power supply point to the logical function portion. The second power trunk line is disposed in an area in which the logical function portion of the chip is disposed. The first power trunk line is disposed between the power supply point and the second power trunk line to connect the second power trunk line with the power supply point. The third trunk line is connected at at least one end to the second trunk line and is disposed in the logical function portion for supplying electric power to the logical function portion.

Abstract: A method of controlling an image memory system wherein non-interlace image data is written into the odd field and the even field memories, and the contents written into the odd field and even field memories are respectively read out so as to be converted into interlace image data. Each line of the non-interlace image data is alternately written into the odd field and even field memories in units of a plurality of dots. If the plurality of dots include dots for the odd field and dots for the even field, the image data of the plurality of dots are simultaneously written into both the odd field memory and the even field memory. When reading the image data out from the odd field memory, the image data for the even field written into the odd field memory is invalidated. Similarly, when reading the image data out from the even field memory, the image data for the odd field written into the even field memory is invalidated.

Abstract: A regenerative repeater for regeneratively repeating a signal to be transmitted is inserted in two ring-like transmission lines, and is provided with loop back means for automatically separating the regenerative repeater from the ring-like transmission lines in the condition that a power supply is in a not-yet-turned-on state, so that closed ring-like transmission lines are formed in the form where the regenerative repeater is removed in the condition that the power supply is in the not-yet-turned-on state.

Abstract: A bonding method and apparatus for bonding a wire material having a ball-like end on a bonding pad is disclosed. While the ball of the wire material on the bonding pad is being pressed by a bonding tip, an ultrasonic wave and a high frequency current are applied in combination to the bonding tip so as to improve strength of the bonding portion.