Patents Assigned to Hitachi Hokkai Semiconductor, Ltd.
  • Publication number: 20140084440
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Application
    Filed: November 26, 2013
    Publication date: March 27, 2014
    Applicants: HITACHI HOKKAI SEMICONDUCTOR LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
  • Patent number: 8618642
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 31, 2013
    Assignees: Renesas Electronics Corporation, Hitachi Hokkai Semiconductor Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Publication number: 20120007224
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Applicants: HITACHI HOKKAI SEMICONDUCTOR LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
  • Publication number: 20120007225
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Applicants: HITACHI HOKKAI SEMICONDUCTOR LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
  • Patent number: 8044509
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: October 25, 2011
    Assignees: Renesas Electronics Corporation, Hitachi Hokkai Semiconductor Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Publication number: 20110095412
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Application
    Filed: December 30, 2010
    Publication date: April 28, 2011
    Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI HOKKAI SEMICONDUCTOR, LTD.
    Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
  • Patent number: 7911054
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: March 22, 2011
    Assignees: Renesas Electronics Corporation, Hitachi Hokkai Semiconductor Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 7805562
    Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: September 28, 2010
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Naoki Yada, Eiichi Ishikawa
  • Publication number: 20090189260
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Application
    Filed: March 25, 2009
    Publication date: July 30, 2009
    Applicants: RENESAS TECHNOLOGY CORP., HITACHI HOKKAI SEMICONDUCTOR, LTD.
    Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
  • Patent number: 7518156
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: April 14, 2009
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Patent number: 7310700
    Abstract: The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its processing. An erase and program control program for an electrically erasable and programmable non-volatile memory is configured inclusive of a loop of the application of a high voltage pulse and data verify or the like, for example. If a program jumped to a subroutine for an address specified by a user is programmed in advance during this loop, then a process by a CPU can be temporarily jumped to the subroutine for the user defined address. Thus, erase and programming can be effected on a system which needs to confirm internal and external events every predetermined intervals or a system with a learning function, or the like during the execution of a user program.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: December 18, 2007
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Naoki Yada, Eiichi Ishikawa
  • Patent number: 7277979
    Abstract: A microcomputer capable of on-board programming of dedicated user communication protocols without requiring a serial interface on the mounted board, and that will not destroy the dedicated user communication protocol code even if the system runs out of control. A user boot mat other than a user mat is provided for programming control programs for the user in the on-chip non-volatile memory of the microcomputer. The user boot mat serves as the mat for programming the dedicated user communication protocol and also provides a user boot mode for running the program. The user boot mat cannot program or erase in this user boot mode. By separating the user boot mat and user mat, an interface capable of programming and erasing the user-specified programming can be achieved without having to program a dedicated communication protocol on the user mat.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: October 2, 2007
    Assignees: Renesas Technology Corporation, Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Naoki Yada, Eiichi Ishikawa
  • Patent number: 7253011
    Abstract: Provided is a fabrication method of a semiconductor integrated circuit device, which comprises disposing, in a ultrapure water preparing system, UF equipment having therein a UF module which has been manufactured by disposing, in a body thereof, a plurality of capillary hollow fiber membranes composed of a polysulfone membrane or polyimide membrane, bonding the plurality of hollow fiber membranes at end portions thereof by hot welding, and by this hot welding, simultaneously adhering the hollow fiber membranes to the body. Upon preparation of ultrapure water to be used for the fabrication of the semiconductor integrated circuit device, the present invention makes it possible to prevent run-off of ionized amine into the ultrapure water.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: August 7, 2007
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Osamu Takahashi, Kunio Ogasawara
  • Patent number: 7199469
    Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 3, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Toru Ishida, Tetsuharu Urawa, Fujio Ito, Tomoo Matsuzawa, Kazunari Suzuki, Akihiko Kameoka, Hiromichi Suzuki, Takuji Ide
  • Patent number: 7194571
    Abstract: The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its processing. An erase and program control program for an electrically erasable and programmable non-volatile memory is configured inclusive of a loop of the application of a high voltage pulse and data verify or the like, for example. If a program jumped to a subroutine for an address specified by a user is programmed in advance during this loop, then a process by a CPU can be temporarily jumped to the subroutine for the user defined address. Thus, erase and programming can be effected on a system which needs to confirm internal and external events every predetermined intervals or a system with a learning function, or the like during the execution of a user program.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 20, 2007
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Naoki Yada, Eiichi Ishikawa
  • Patent number: 7093042
    Abstract: A process program such as an erasing/programming program is stored in a boot mat in a nonvolatile memory operational in a boot mode specified after reset start, and a transfer control program for the process program is also stored therein in advance. With an action of setting control information to a predetermined register as trigger, the state of an on-chip CPU is changed from placed in execution of an optional user program to enabled for execution of a transfer control program in the boot mat, and the CPU is returned to the re-execution state of the optional program, after the process program is transferred to an on-chip RAM.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: August 15, 2006
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Toshihiro Matsuo, Hiromichi Ishikura, Hirofumi Mukai, Naoki Yada
  • Patent number: 7015119
    Abstract: A method of fabrication of a semiconductor integrated circuit device, calls for disposing, in an ultrapure water preparing system, UF equipment having therein a UF module which has been manufactured by disposing, in a body thereof, a plurality of capillary hollow fiber membranes composed of a polysulfone membrane or polyimide membrane, bonding the plurality of hollow fiber membranes at end portions thereof by hot welding, and by this hot welding, simultaneously adhering the hollow fiber membranes to the body. Upon preparation of ultrapure water to be used for the fabrication of the semiconductor integrated circuit device, it is possible to prevent run-off of ionized amine into the ultrapure water.
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: March 21, 2006
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Osamu Takahashi, Kunio Ogasawara
  • Patent number: 7015070
    Abstract: A method of manufacturing an electronic device including a first electronic component mounted on one main surface of a wiring board by being thermo-compression bonded by means of a thermo-compression bonding tool with an adhesive resin interposed between a first area of the one main surface of the wiring board and the first electronic component, and a second electronic component mounted on a second area different from the first area of the one main surface of the wiring board by melting a soldering paste material and higher than the first electronic component in post-mounting height, and wherein the first electronic component is mounted before the mounting of the second electronic component.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: March 21, 2006
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventor: Shigeru Nakamura
  • Patent number: 6974710
    Abstract: A method of fabricating a semiconductor integrated circuit device includes performing a wafer process to a plurality of wafers so as to form a plurality of semiconductor integrated circuit devices over each of the wafers, performing a first electrical test to a first set of wafers selected from the plurality of wafers formed in the wafer process and accommodated in a first wafer cassette placed in a wafer prober, and performing a second electrical test to a second set of wafers selected from the plurality of wafers formed in the wafer process and accommodated in a second wafer cassette placed in the wafer prober by automatically changing a test object to the second set of wafers.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: December 13, 2005
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventor: Tomohiro Taira
  • Patent number: 6951774
    Abstract: A semiconductor device having a stack structure comprises: a single-piece substrate having a chip support surface serving as a main surface, a back surface, a plurality of connection terminals provided on the chip support surface and a plurality of solder balls provided on the back surface; a first semiconductor chip having a main surface, aback surface, a plurality of semiconductor devices on the main surface of the first semiconductor chip and a plurality of pads provided on the main surface of the first semiconductor chip; a second semiconductor chip having a main surface, a back surface, a plurality of semiconductor devices provided on the main surface of the second semiconductor chip and a plurality of pads provided on the main surface of the second semiconductor chip; and a resin sealing body formed on the chip support surface of the single-piece substrate and used for sealing the first semiconductor chip and the second semiconductor chip; and a plurality of wires for connecting the pads of the second s
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: October 4, 2005
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Shigeru Nakamura, Masakatsu Gotou