Abstract: A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor connected to a gate signal line, and a region of the transparent oxide layer other than at least a channel region portion directly below the gate electrode is converted into an electrically conductive region, and a source signal line, a source region portion of the thin film transistor connected to the source signal line, a pixel electrode, and a drain region portion of the thin film transistor connected to the pixel electrode are formed from the conductive region.

Abstract: A liquid crystal display device is provided which can enhance a numerical aperture. The display has a pixel transparent conductive film electrode and a transparent conductive film counter electrode formed on an insulation film, which in turn is formed on a first substrate to cover the pixel electrode. A plurality of linear portions of the counter electrode are arranged on the pixel electrode. A gate-signal-line side of the pixel electrode of the first pixel is formed on a first-pixel side of the gate signal line and a gate-signal-line side of the pixel electrode of the second pixel is formed on a second-pixel side of the gate signal line. The gate-signal-line-side frame portion of the counter electrode of the first pixel and the gate-signal-line-side frame portion of the counter electrode of the second pixel are formed in common on the gate signal line in a striding manner.

Abstract: In a display device which includes a driver circuit having a shift register circuit, the shift register circuit is constituted of basic circuits in plural stages. Each basic circuit is constituted of a circuit A, a circuit B and a circuit C. The circuit A fetches a first drive clock (or a second drive clock) inputted from the outside when transfer data is inputted to the circuit A from a circuit of preceding stage, outputs the transfer data as a shift output of own stage, and transfers the transfer data to the circuit B. The circuit B transfers the transfer data to the circuit A of the basic circuit of the succeeding stage, and resets the circuit C. The circuit C resets the circuit A and the circuit B in synchronism with the first drive clock (or the second drive clock) generated at next timing or succeeding timing of the first drive clock.