Patents Assigned to Hitachi, Ltd.
  • Publication number: 20240168859
    Abstract: A software performance verification system extracts a partial code as part of a code of a program configuring software, generates a feature vector based on the partial code, and generates, as a verification result of the partial code, information based on output obtained from a performance verification model through input of the partial code as a verification target to the performance verification model that is a machine learning model having been trained by use of learning data that includes the feature vector of the partial code for learning and performance information indicative of the performance of software implemented on the basis of the partial code. The software performance verification system generates, for example, a feature vector having metrics values acquired from the partial code as the elements of the feature vector. The performance verification model outputs, for example, the probability of there being a problem with a process to be implemented on the basis of the partial code.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 23, 2024
    Applicant: Hitachi, Ltd.
    Inventors: Menglong YANG, Kyohei OYAMA, Daisuke SHIMBARA
  • Publication number: 20240169816
    Abstract: A work detection determination system performs detection determination on a work with high accuracy.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 23, 2024
    Applicant: Hitachi, Ltd.
    Inventors: Tetsuya ISHIMARU, Hiroyuki YOSHIMOTO, Yoshihiro WAKISAKA, Nobuyuki SUGII
  • Patent number: 11989455
    Abstract: A storage system includes a plurality of storage nodes 4 each having one or more storage devices. The storage node includes a CPU. The CPU is configured to select a priority path to be notified as a usable path to a higher-level apparatus among paths which allows access of a predetermined logical unit to which a storage area of the storage device is provided from the higher-level apparatus. The CPU is configured to send the priority path as a reply to an inquiry about a path to the predetermined logical unit from the higher-level apparatus.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: May 21, 2024
    Assignee: HITACHI, LTD.
    Inventors: Shinri Inoue, Kouji Iwamitsu, Takao Totsuka
  • Patent number: 11989079
    Abstract: A system management device manages a monitored system. When a performance failure occurs in the monitored system, the system management device creates a plurality of countermeasures for the performance failure. The system management device evaluates, for each of the plurality of countermeasures, the influence of the countermeasure on the execution of a job having an execution deadline associated with the countermeasure. The system management device selects the countermeasure to be executed on the monitored system from out of the plurality of countermeasures based on the evaluation results.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: May 21, 2024
    Assignee: HITACHI, LTD.
    Inventors: Aiko Tanaka, Kazuki Ootsubo, Yasuaki Saito
  • Patent number: 11989105
    Abstract: In a storage system, a failover time is shortened while avoiding erroneous detection of a node failure according to network quality. The storage system includes a plurality of storage nodes having processors; a data storage device; the plurality of storage nodes having the processors for processing data to be input to and output from the storage device; and a network for connecting the plurality of storage nodes, wherein the plurality of storage nodes monitors the operation status of each other to perform node failure detection for determining the occurrence of a failure of the storage node on the basis of a time-out value, performs a failover process in which one of the other storage nodes takes over the process of the storage node when the failure occurs in the storage node, and adjusts the time-out value on the basis of the status of the network between the storage nodes.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: May 21, 2024
    Assignee: HITACHI, LTD.
    Inventors: Misato Yoshida, Takaki Nakamura, Takahiro Yamamoto, Masakuni Agetsuma
  • Patent number: 11986986
    Abstract: Provided is an injection molding system capable of improving usability for a user. The injection molding system determines a combination of a mold and an injection molding machine and a specific molding condition specific to the combination of the mold and the injection molding machine, and outputs the determined specific molding condition in a predetermined form for manual input to the injection molding machine.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: May 21, 2024
    Assignee: Hitachi, Ltd.
    Inventors: Ryotaro Shimada, Satoshi Arai
  • Patent number: 11989412
    Abstract: A storage system includes a CPU, a first memory module, a second memory module, and a storage device. The processor and the first memory module are installed in the same node. The second memory module are replaceable without shutting down power supply of the node. The first memory module stores an operating system and a program for managing user data to be stored in the storage device. The second memory module stores cache data of the user data to be stored in the storage device. The processor is configured to store a copy of data to be stored in the second memory module in the third memory module.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: May 21, 2024
    Assignee: HITACHI, LTD.
    Inventor: Norio Chujo
  • Patent number: 11989623
    Abstract: The present invention aims at enabling a gate-type quantum computer to deal with actual problems. There is provided a quantum computer including: a quantum register holding qubits, a control gate performing an operation on the quantum register, and a readout unit observing a state of the quantum register; and the quantum computer repeating longitudinal relaxation to the ground state by gradually changing Hamiltonian H(t) for a predetermined time, wherein the unitary operation determined by the Hamiltonian H(t) at each time is performed with the control gate for a time of about a longitudinal relaxation time, the quantum state is relaxed every time of about the longitudinal relaxation time, and the ground state prepared for an initial state is time-evolved to the ground state of the Hamiltonian which is defined as a problem.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: May 21, 2024
    Assignee: HITACHI, LTD.
    Inventor: Tatsuya Tomaru
  • Patent number: 11987452
    Abstract: A plurality of workpieces include a plurality of first workpieces of a first workpiece group to be loaded onto a first loaded member according to a first loading sequence and a plurality of second workpieces of a second workpiece group to be loaded onto a second loaded member according to a second loading sequence. On a conveying device, workpieces are arranged at ransom with respect to respective arrangement sequences of the first workpiece group and the second workpiece group and the classifications of the first workpiece group and the second workpiece group. On a conveying device, workpieces of the first workpiece group are sequentially arranged based on the first loading sequence and workpieces of the second workpiece group are sequentially arranged based on the second loading sequence. At the same time, the workpieces of the first workpiece group and the second workpiece group are arranged together.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 21, 2024
    Assignee: HITACHI, LTD.
    Inventors: Sanato Nagata, Kei Utsugi, Nobutaka Kimura
  • Publication number: 20240162297
    Abstract: A silicon carbide semiconductor device includes: a trench formed on an upper surface of a silicon carbide semiconductor substrate; a gate electrode in the trench; an n-type drift layer, a p-type guard region, an n-type semiconductor region to which a source potential is applied, a p-type body layer and an n-type current diffusion region that have a lower impurity concentration than that of the guard region, the n-type drift layer, the p-type guard region, the n-type semiconductor region, the p-type body layer, and the n-type current diffusion region being formed in the silicon carbide semiconductor substrate; and an n-type JFET region that is formed in the silicon carbide semiconductor substrate so as to be separated from the trench and that connects the current diffusion region and the drift layer. The semiconductor region is separated from the drift layer, the current diffusion region, and the JFET region.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 16, 2024
    Applicant: Hitachi, Ltd.
    Inventors: Takeru SUTO, Keisuke KOBAYASHI, Tomoka SUEMATSU, Haruka SHIMIZU
  • Patent number: 11983526
    Abstract: A software inquiry information management system stores a device request specification in association with a regulation ID that is information specifying a regulation that defines a requirement for receiving legal approval for a vehicle, acquires traceability information of a device that is associated with the device request specification, specifies a regulation ID corresponding to the device request specification that is associated with the acquired traceability information, generates approval software inquiry information that is information in which the specified regulation ID is associated with one or more software IDs included in the traceability information, and generates vehicle traceability information that is information in which the approval software inquiry information is associated with the traceability information.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: May 14, 2024
    Assignee: HITACHI, LTD.
    Inventor: Hidetoshi Teraoka
  • Patent number: 11983002
    Abstract: The problem of the present invention is to establish how to more accurately estimate the failure probabilities of the components of a machine system that has a small number of failure records.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: May 14, 2024
    Assignee: Hitachi, Ltd.
    Inventors: Hiroaki Amakawa, Yosuke Ueki, Takahide Shinge
  • Patent number: 11982998
    Abstract: A manufacturing monitoring assistance device includes: a model creation unit creating a computation model when a product as a sample is normal, based on a three-dimensional form acquired from the product; a simulation unit creating a corrective computation model when the product is abnormal, by adding a sample of an abnormal portion in the product to the created computation model, and performing a simulation on each of the computation model and the corrective computation model; and a monitoring method determination unit determining a method for monitoring a manufacturing process for the product, based on an abnormality index being a difference between an output from a sensor as a result of the simulation performed on the computation model and an output from a sensor as a result of the simulation performed on the corrective computation model, and causing an output device to display the determined method and the abnormality index.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: May 14, 2024
    Assignee: HITACHI, LTD.
    Inventors: Masanori Kitaoka, Hisashi Endou, Nobuhiro Kakeno, Hiroshi Yoshikawa, Toshihiro Yamada
  • Patent number: 11982992
    Abstract: Example implementations described herein involve systems and methods that can involve extracting features from each of a plurality of time-series sensor data, the plurality of time-series sensor data associated with execution of one or more operations; clustering the extracted features into a plurality of tasks that occur from execution of the one or more operations, each of the plurality of tasks associated with a clustering identifier (ID) from the clustering; and calculating a cycle time of the cycle based on the initiation and end of the cycle recognized by referencing a cycle pattern model, wherein the cycle pattern model comprises configuration information of a cycle including a set from a plurality of the clustering IDs.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 14, 2024
    Assignee: HITACHI, LTD.
    Inventors: Yasutaka Serizawa, Sudhanshu Gaur
  • Patent number: 11985792
    Abstract: An enclosure of an electronic computing apparatus allows two electronic computing modules, each having a built-in fan, to be mounted in a perpendicular direction, when the two electronic computing modules are inserted, a shutter is at an intermediate position due to an elastic force of pushing a spring cover in a front surface direction, from push rods corresponding to the two electronic computing modules, and when one of the electronic computing modules is removed, the elastic force of pushing the cover from the push rod on the removal is lost, and the shutter moves, around a rotating mechanism, to a side of a housing space on the removal side and shuts off a flow path in the housing space.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: May 14, 2024
    Assignee: HITACHI, LTD.
    Inventors: Sho Ikeda, Osamu Kamimura, Kenichi Miyamoto, Akihiro Adachi
  • Patent number: 11977866
    Abstract: There is provided an application screen display program implementation method for executing application software to display a screen using an information processing apparatus. Each record of a master table for controlling the display of each display element for display elements configuring a screen and transaction data input and output from the display element has a field for holding an index of an array, and association with an index of an array in a source code of an execution program is performed. Therefore, in application development, the required man-hours with respect to the change of the display screen are reduced.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventor: Kiyoko Koizumi
  • Patent number: 11977487
    Abstract: In a management node that manages a distributed file and object storage that accessibly manages a file used by an application, the distributed file and object storage is accessible to a file managed by a storage of another site, and a management node includes a processor, and the processor is configured to specify an access circumstance relating to a file by an application, and control caching by the distributed file and object storage of the own site with respect to the file managed by the storage of the other site used by the application, before the application is executed, based on the access circumstance.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventors: Shimpei Nomura, Mitsuo Hayasaka
  • Patent number: 11977636
    Abstract: Example implementations described herein provide systems and methods for detecting damage to data by malware and involve generating log information at a storage device based on a write input/output (I/O) provided to the storage device by one or more servers, the log information comprising time information for storing the write I/O to the storage device, logical block information for the write I/O, and a compression ratio associated with storing the write I/O to the storage device; and, for a request by a management server to provide the log information for a specified time range for the storage device, returning, from the storage device, the logical block information and the compression ratio associated with the time information within the specified time range.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventor: Tomohiro Kawaguchi
  • Patent number: 11978794
    Abstract: In a SiC power MISFET having a lateral surface of a trench formed in an upper surface of a SiC epitaxial substrate as a channel region, a silicon carbide semiconductor device having low resistance, high performance, and high reliability is realized. As a means therefor, a SiC power MISFET is formed as an island-shaped unit cell on an upper surface of an n-type SiC epitaxial substrate that is provided with a drain region on a bottom surface thereof, the SiC power MISFET including: an n-type current diffusion region that surrounds a p-type body layer contact region and an n-type source region in the indicated order in a plan view; a p-type body layer and an n-type JFET region; a trench that is formed on the body layer so as to span between the source region and the current diffusion region adjacent each other in a first direction and extends in the first direction; and a gate electrode embedded in the trench with a gate insulating film therebetween.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventors: Takeru Suto, Naoki Tega, Naoki Watanabe, Yuki Mori, Digh Hisamoto
  • Patent number: 11977433
    Abstract: Aspects of the present disclosure involve an innovative method for detecting error zones from a plurality of volume groups. The method may include creating a plurality of probe groups for error detection; detecting a new error associated with the plurality of probe groups and the plurality of volume groups; retrieving error information associated with the new error, wherein the error information comprises an error source, an error type, and an error time; retrieving an error correlation rule associated with the error information; determining if the error correlation rule is satisfied by the error information and information of other known errors; and identifying a common zone based on the error information and the information of the other known errors as an error zone.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventors: Hiroyuki Osaki, Tomohiro Kawaguchi