Patents Assigned to Hitachi, Ltd.
  • Patent number: 8896273
    Abstract: Lower order control devices control plural battery cells configuring plural battery modules. An input terminal of the low order control device in the highest potential, an output terminal of the low order control device in the lowest potential, and a high order control device are connected by isolating units, photocouplers. Diodes which prevent a discharge current of the battery cells in the battery modules are disposed between the output terminal of the low order control device and the battery cells in the battery module on the low potential side. Terminals related to input/output of a signal are electrically connected without isolating among the plural low order control devices.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: November 25, 2014
    Assignees: Hitachi, Ltd., Shin-Kobe Electric Machinery Co., Ltd.
    Inventors: Hideki Miyazaki, Akihiko Emori, Akihiko Kudo, Tsuyoshi Kai
  • Patent number: 8895186
    Abstract: It is an objective of the present invention to provide a lithium-ion rechargeable battery anode which can control the volume change of a primary particle of a negative-electrode active material other than a carbon-based material and that can prevent cracks due to stress caused by the volume change from occurring and extending. There is provided an anode for a lithium-ion rechargeable battery including a primary particle of a negative-electrode active material, a conductive material, and a binder, the negative-electrode active material including at least one of silicon and tin, and at least one element selected from elements that do not chemically react with lithium, in which holes are present both in an inner core region in the central region of the primary particle of the negative-electrode active material and in a periphery region that covers the inner core region.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Nakabayashi, Shin Takahashi, Motoki Ohta, Yoshihito Yoshizawa
  • Patent number: 8898675
    Abstract: The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
  • Patent number: 8898649
    Abstract: Disclosed is a method for analyzing a program that includes database operation statements, including: a first procedure for analyzing control flow of a program and data used in the program, on the basis of the program and the execution result of the program; a second procedure for analyzing the dependency relationship among a plurality of database operation statements, in accordance with the analysis result of the first procedure and the operation details of the plurality of database operation statements; a third procedure for analyzing the propagation path of the incorrect operation in the opposite direction to the control flow, on the basis of the analysis result of the first procedure and the analysis result of the second procedure and taking as a starting point for analysis a predetermined program location which is operating incorrectly; and a fourth procedure for displaying program statements on the propagation path obtained by the third procedure.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Hiroyasu Nishiyama
  • Patent number: 8898545
    Abstract: A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Tsunehiro, Akifumi Suzuki, Junji Ogawa
  • Patent number: 8898189
    Abstract: In a system manages a plurality of pieces of sensor information in a plant, or the like, it can be reducing an amount of data stored in a database and easily a processing for searching a place of an anomaly and an anomaly cause. A database management method for use in a computer for managing a database, the database management method including: a step of analyzing a query; a step of generating a first inquiry for searching the database for compressed data; a step of generating a second inquiry for executing a search of time-series data; a step of extracting given data from the obtained time-series data, based on a response result of the second inquiry; and a step of generating an output result by extracting data to be output to a client computer from the given data.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Sadaki Nakano, Keiro Muro, Shinji Fujiwara
  • Patent number: 8897006
    Abstract: First and second units are mounted on a rear side of a housing of a storage system. Either of the first and second units includes a fan. The rear side of the housing includes an upper-tier portion defining an upper-tier opening, and a lower-tier portion defining a lower-tier opening, and the housing further includes a boundary portion that is a boundary between the upper-tier portion and the lower-tier portion, and a shutter unit. The boundary portion includes a first through hole that is a through hole connecting an upper-tier passage and a lower-tier passage. When the fan is operating, if the first unit is removed from the upper-tier portion, the shutter unit blocks the upper-tier passage, and if the second unit is removed from the lower-tier portion, the shutter unit blocks the lower-tier passage.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Takuji Ito, Akihiro Inamura, Tsuyoshi Sasagawa
  • Patent number: 8896261
    Abstract: The excitation overcurrent detection unit for the doubly-fed electric machine is provided with a function to determine an excitation current magnitude relationship among three phases. The firing pulse is held to on-state or off-state to cause the largest-current phase and the second-largest-current phase to charge the DC capacitor by the operation of diodes. The conduction ratio of the third-largest-current phase or minimum current phase is controlled according to the detected current value to protect against a possible short-circuit across the DC capacitor. When the voltage of the DC capacitor exceeds a preset value, the voltage is suppressed by operating active or passive power devices.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akira Bando, Masaya Ichinose, Yasuhiro Kiyofuji, Yasuaki Nakayama
  • Patent number: 8897161
    Abstract: To reduce an uplink interference in a network with a first base station of a large output and a second base station of a small output. Detecting the interference, the second base station urges the first base station to hand over a terminal causing it to the second base station. Multiple base stations and one or more terminals exist in this system, each terminal connects with one base station, and a serving base station is changed according to a communication state of each terminal. If the different second base station other than the first base station to which the terminal connects detects a large interference, the second base station will multicast transmit information for urging handover to the base stations except itself. The base station having received the information specifies a terminal giving the interference to the second base station, and makes it to be handed over thereto.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Kenzaburo Fujishima, Tsuyoshi Tamaki, Rintaro Katayama, Hitoshi Ishida
  • Patent number: 8897644
    Abstract: Technology to provide linked control of bandwidth allocation to a plurality of optical network units among the plural wavelengths by a bandwidth allocation section coupled to the plural optical network units.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Jun Sugawa, Daisuke Mashimo, Hiroki Ikeda
  • Patent number: 8896027
    Abstract: Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current.
    Type: Grant
    Filed: November 24, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Terano, Kazuhiro Mochizuki, Tomonobu Tsuchiya
  • Patent number: 8898384
    Abstract: A computerized data storage system includes at least one storage device including a nonvolatile writable medium; a cache memory and a data management controller and a storage port. The storage port is operable to receive a request to read data, and, in response to the request to read data, to send the data stored in the data storing area of the cache memory. The storage port is further operable to receive a request to write data, and, in response to the request to write data, to send the write data to the data storing area of the cache memory. The storage system further includes a thin provisioning controller operable to provide a virtual volume, and a capacity pool. The storage system further includes a data compression controller and a data decompression controller.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Tomohiro Kawaguchi
  • Patent number: 8898383
    Abstract: A storage controller calculates an access frequency of each logical disk; that is selects a first logical disk device of which the access frequency exceeds a first predetermined value, the first logical disk device being allocated to a first physical disk device; selects a second logical disk device which has the access frequency equal to or less than a second predetermined value, the second logical disk device being allocated to a second physical disk device; and reallocates the first and second logical device; and reallocates the first and second logical devices to the second and the first physical disk device, respectively.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yasutomo Yamamoto, Akira Yamamoto, Takao Satoh
  • Publication number: 20140343959
    Abstract: It is provided an analysis system comprising: an input unit to receive a medical cost of a insured person, intervention information on a provision of an intervention service and a start date of the intervention service; a propensity score calculation unit to analyze a relationship between the medical cost before the provision of the intervention service and the intervention information, and to calculate a propensity score of an intervention group and a propensity score of a nonintervention group; and an adjusted medical cost calculation unit to calculate adjusted medical costs of the intervention group before and after the provision of the intervention service by using the propensity score of the intervention group and medical costs of the intervention group before and after the provision of the intervention service, and to calculate adjusted medical costs of the nonintervention group before and after the provision of the intervention service.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 20, 2014
    Applicant: HITACHI, LTD.,
    Inventors: Yasutaka HASEGAWA, Hideyuki BAN, Naofumi TOMITA
  • Publication number: 20140344503
    Abstract: Example implementations described herein are directed to implementation of the atomic write feature in the storage system setting. Example implementations may utilize flash memory to facilitate or to form atomic write commands to improve flash memory performance and endurance. Several protocols involving the cache unit of the storage system may include managing a status of the storage system so that data corresponding to an atomic write command are stored in a cache unit, with old data maintained in the storage system until the write data corresponding to an atomic write command is properly received.
    Type: Application
    Filed: May 17, 2013
    Publication date: November 20, 2014
    Applicant: HITACHI, LTD.
    Inventors: Akira DEGUCHI, Akiko NAKAJIMA
  • Publication number: 20140343965
    Abstract: It is provided an analysis system comprising: a causation/transition structure calculating unit generating a graph structure including a node and a probability variable relating to item, and a probabilistic dependency defined by one of a directed link or an undirected link between the nodes; a node generating unit generating an event space of the nodes; a probability calculating unit calculating a conditional probability of the graph structure; a state transition model reconstructing unit reconstructing a state transition model with a graph structure, an event space and a conditional probability including specified probability variables based on a state transition model; a disease state transition estimating unit estimating a disease state transition probability based on the reconstructed state transition model; and a health guidance supporting unit selecting a subject for health guidance and a content of health guidance based on the estimated disease state transition probability.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 20, 2014
    Applicant: HITACHI, LTD.
    Inventors: Toshinori MIYOSHI, Yasutaka HASEGAWA, Hideyuki BAN, Takeshi NAGASAKI, Hiroshi SHINJO
  • Publication number: 20140343966
    Abstract: It is provided an analysis system comprising a processor executing a program and a memory storing the program. The analysis system further comprises a data mapping unit controlling the processor to set an attractive force and a repulsive force acting between the instances based on the similarity information between data, and arranging the instances in a vector space having a certain number of dimensions so that an energy caused by the attractive force and the repulsive force is less than a threshold defined in advance, and a clustering unit classifying the instances arranged in the vector space. The data mapping unit is configured to virtually add one dimension to the vector space, add a minute fluctuation to coordinates of the instances in a direction of the added dimension, and calculate a minimum number of dimensions of the vector space where the instances are stable with respect to the minute fluctuation.
    Type: Application
    Filed: May 15, 2014
    Publication date: November 20, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Toshinori MIYOSHI, Yasutaka HASEGAWA, Hideyuki BAN, Takeshi NAGASAKI, Hiroshi SHINJO
  • Publication number: 20140338487
    Abstract: In a roller screw (1) having a screw shaft (2), a plurality of rollers (4) that roll on a flank face (21a) of the screw shaft; and a cage (3) that rotatably houses the plurality of rollers, a plurality of roller groups (40) each having a plurality of rollers arranged at equal intervals while contacting with the same flank face along a spiral groove of the screw shaft for one lead are provided, and the plurality of roller groups are arranged at intervals in the axial direction of the screw shaft. With this configuration, the size of the nut portion in the axial direction of the screw shaft can be prevented from being bloated, and the load distribution in a circumferential direction of the screw shaft can be uniformized.
    Type: Application
    Filed: December 14, 2011
    Publication date: November 20, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Hiroyuki Yamada, Isao Hayase
  • Publication number: 20140344534
    Abstract: A system having an SMP connection made among each information processing apparatus in units of a module including a CPU, a main memory, an HDD and the like, allows use of the HDDs distributed in the system as a single disk. The SMP connection is made among information processing apparatuses each including one or more CPUs, a main memory, one or more storage devices, and a storage device controller that controls the storage device. The storage device controller in a certain information processing apparatus controls the storage device in the information processing apparatus and the storage device in another information processing apparatus. Each information processing apparatus includes a storage device switch for exclusively switching which of the storage device controller in the information processing apparatus and the storage device controller in another information processing apparatus is connected to the storage device in the information processing apparatus.
    Type: Application
    Filed: December 26, 2012
    Publication date: November 20, 2014
    Applicant: HITACHI, LTD.
    Inventors: Koichiroh Kato, Akihiro Umezawa, Nobuo Yagi
  • Publication number: 20140344510
    Abstract: In an exemplary storage system, a processor assigns an unused process to a read request designating an area of a logical volume. The processor determines whether the data designated by the read request is in a cache memory, based on a first identifier for identifying the area designated by the read request. When the designated data is not in the cache memory and a part of physical volumes providing the logical volume is a first kind of physical volume, the processor stores the first identifier associated with an identifier for identifying an area allocated in the cache memory. When the designated data is not in the cache memory and a part of the physical volumes is a second kind of physical volume, the processor stores a second identifier for identifying the process assigned to the read request associated with an identifier for identifying an area allocated in the cache memory.
    Type: Application
    Filed: July 29, 2014
    Publication date: November 20, 2014
    Applicant: Hitachi, Ltd.
    Inventors: TOMOHIRO YOSHIHARA, Akira DEGUCHI, Hiroaki AKUTSU