Abstract: An asynchronous signal synchronizing circuit for sampling and external asynchronous signal in a quarter of the period of a clock. A first latch circuit latches asynchronous input signal in accordance with a first clock, and a second latch circuit latches the output of the first latch circuit in accordance with a second clock having a phase shift 180.degree. out of phase with the first clock. A third latch circuit latches the output signal of the second latch signal in accordance with a clock signal that represents the inverse of the first clock. A fourth latch circuit latches the output signal of the third latch circuit under the control of a clock that corresponds to the inverse of the second clock. The asynchronous input signal is sampled at the tailing edge of the first clock signal and validated by the tailing edge of the second clock signal. The synchronization of the asynchronous signal can thus be performed in a quarter of a clock cycle.

Abstract: A memory circuit is divided into a plurality of memory blocks, and an address register and a delay register are disposed in each memory block. Therefore, a read or write operation and a shifting operation of the address for storing data inside a memory matrix can be realized by a pipeline technique, and hence a memory circuit having a high processing speed is obtained.

Abstract: To reduce the power dissipation of a static random access memory, a write enable signal is applied to the gates of load MOS transistors on bit lines which are connected to a memory cell. During the write-in time, the load MOS transistors are turned off so as to prevent as electric current from flowing from a power source into the earth through the memory cell.

Abstract: In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.A memory cell capable of extremely large scale integration can be obtained.

Abstract: Disclosed is a PCM coder-decoder having a construction such that a digital filter contained originally in the PCM coder-decoder is utilized on the time division basis in order to fold back a digital reception signal to a digital signal transmission side and thus to accomplish interruption, communication exchange between three parties, gain control, fold-over test of the PCM signal, and so forth, in addition to the coding and decoding functions inherent to the PCM coder-decoder.

Abstract: A pulse width modulation circuit which can cancel the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits to an existing pulse width modulation circuit. The invention relates also to an integration circuit of the product of two analog signals using the pulse width modulation circuit described above.The principle of the present invention combines a circuit for cancelling the offset of a triangular wave signal by inverting either the triangular wave signal with respect to an input signal or the input signal with respect to the triangular wave signal, in every predetermined period, with a circuit for eliminating the offset of a comparator by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

Abstract: In a multiprocessor system, a data transferring port into which data can be written only when no data is stored and from which data can be read only when it is stored is provided, and the port itself is caused to perform an exclusion control, whereby that processor of a plurality of processors which has once acquired a bus mastership is prevented from making another bus use request until the bus use requests of the other processors run out.