Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Abstract: A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode.

Abstract: A memory architecture includes a virtual memory system and a physical memory system. For one mode of operation all memory accesses are performed within the virtual memory system. For a second mode of operation, accesses within a range of shadowed addresses are redirected to the physical memory system. Addresses outside of the range of shadowed addresses are still performed by the virtual memory system.

Abstract: A remote user interface system for use with a host computer is provided. The remote user interface system includes a host transceiver system attached for communication with a host computer system. The remote user interface system also includes a portable interface tablet having a touchscreen display. Functionally, the host transceiver system gathers audio and video output generated by the host computer system. The audio and video output are sent by the host transceiver system to the portable interface tablet for output to the user. The portable interface tablet also gathers mouse and audio input from the user. These inputs are sent by the portable interface tablet to the host transceiver system and injected into the host computer system as user input.

Abstract: An independent memory architecture is provided which includes a plurality of multi-line channels each capable of carrying either data or address information to a plurality of independent memory clusters. The channels operate independently to access and store data in separate ones of the memory clusters. The independent operation enables faster and more efficient utilization within a memory device over any prior art memory architecture. Each of the clusters have one or more independently addressable memory banks respectively having a plurality of data storage locations organized into respective arrays with each of the storage locations having a distinct column and row address.

Abstract: An independent and cooperative memory architecture is provided which includes a plurality of multi-line channels each capable of carrying either data or address information to a plurality of independent memory clusters. The channels can either operate independently to access and store data in separate ones of the memory clusters, or cooperatively to access and store data in one of the memory clusters. The independent and cooperative operation enables faster and more efficient utilization within a memory device over any prior art memory architecture. Each of the clusters have one or more independently addressable memory banks respectively having a plurality of data storage locations organized into respective arrays with each of the storage locations having a distinct column and row address. The multi-line channels provide a plurality of distinct operating modes for conducting selected data read and/or write transactions within the clusters.

Abstract: A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode.

Abstract: A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.

Abstract: The invention provides a hybrid phase-locked loop (PLL) containing digital and analog portions for digital and analog adjustments, respectively, of an output signal. The hybrid PLL is simple in design. Off-the-shelf controlled oscillators, such as a current controlled oscillator (CCO) can be used with this hybrid PLL. The digital and the analog portions of the hybrid PLL are separate from the controlled oscillator. The digital portion is for a first adjustment of the frequency of the output signal, such as during a calibration. The analog portion is for fine phase and frequency adjustment of the output signal.

Abstract: A fast floating-point multiplication and accumulation unit (fmac) is described. The described fmac uses significantly less hardware, thereby yielding a fast and an inexpensive fmac. This fmac uses an m-bit carry propagation adder instead of a 3 m-bit carry propagation adder and a 2 m-bit normalizer instead of a 3 m-bit normalizer. The normalizer relies on a leading one detection, as opposed to leading one/zero prediction used in known fmac's. Even when the product of the multiplication is opposite in sign to the number added to the product, the fmac, disclosed here, only uses an m-bit adder and a 2 m-bit normalizer.

Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Abstract: A signal transfer circuit for enabling rapids transfer of differential electrical signals among multiple signal paths is provided. The circuit comprises first and second pairs of signal transfer terminals, a pair of internal nodes, first and second pairs of isolation devices, a differential signal amplifier, a gain-enhancing cross-coupled pair of devices, and a precharge circuit. The first and second pairs of isolation devices are of a single device type and are coupled between respective ones of the signal transfer terminal pairs and the internal node pair. The isolation devices each have a control terminal for receiving an isolation control signal. The differential signal amplifier circuit is coupled to the internal nodes, and is comprised of complementary device types. The amplifier circuit has a control terminal for receiving an amplifier control signal for enabling the amplifier circuit.

Abstract: An independent and cooperative memory architecture is provided which includes a plurality of multi-line channels each capable of carrying either data or address information to a plurality of independent memory clusters. The memory architecture includes a slave port for shifting the burden of scheduling and synchronization from a master device to a memory device. By coupling the master device's clock signal to a counter and to an enabler coupled to a FIFO, the slave port makes it possible for the master device to request data from the memory device and to begin clocking out the requested data from the slave port after a fixed number of clock cycles of the master device's clock. The slave port guarantees that data from the memory device is available to the master device following an output access time of the memory device.

Abstract: A method and apparatus for reducing by about half the size of a lookup table containing the partial quotients for radix-4 SRT division with a carry-save adder. The method involves storing in computer memory the positive half of the lookup table and determining partial quotients for negative partial remainders by inverting the data bits of the negative partial remainders and subtracting one therefrom. Then the partial quotients associated with the negative partial remainders are looked up in the positive half of the lookup table by use of the thus computed positive partial remainder and of a selected value of a divisor.

Abstract: A system clock signal is distributed to a plurality of load devices via a plurality of phase correction circuits each coupled to a different pair of a plurality of pairs of clock signal conductors. The proximal end of one of the pair of conductors is coupled to the output of a delay line and receives a phase corrected version of the system clock signal. The distal end of this conductor is coupled to the load device at a clock connection node. The clock connection node is fed back to the phase correction circuit via the other one of the pair of conductors. The first and second conductors have equal path lengths in order to provide equal propagation delays. The clock signal fed back from the load device node is coupled as a feedback input to a three input phase detector circuit. The other two inputs are the clock signal output from the phase correction circuit delay line and the system clock signal.

Abstract: A system clock signal is delivered to a plurality of load devices by means of a common loop filter and delay line and a plurality of phase detectors and charge pumps each associated to a different load. The delay line provides a plurality of substantially identical phase corrected clock signals, each clock signal being coupled to the associated load device via an associated conductor member. In one embodiment, each conductor member comprises a loop consisting of a pair of conductors having substantially identical path lengths. The phase adjusted clock signals on the proximal end of the outbound conductor are coupled back as a first feedback signal to one input of the associated phase detector. Another feedback signal comprises the clock signal returned from the device node along the second conductor of the pair. A third input to the phase detector is the system input clock signal, which is also coupled to a reference input of the delay line.

Abstract: MOS integrated circuit fabrication processes may be optimized for yield rather than for hot carrier lifetime by compensating for oversize MOS channel lengths with increased V.sub.cc power supply voltage, and by compensating for undersized MOS device channel lengths with decreased V.sub.cc. Where channel lengths are greater than necessary, V.sub.cc is increased to increase switching times, while still operating the integrated circuit in a regime ensuring at least a minimum hot carrier lifetime. A test MOS device is fabricated on the integrated circuit substrate and in a test mode the test device substrate current I.sub.bb is measured. The measured I.sub.bb is then correlated with known I.sub.bb data to ascertain whether the channel length and DC hot carrier lifetime are acceptable, both for the test device and all MOS devices in the integrated circuit. The measured I.sub.bb value may be used with a look-up table to manually adjust the V.sub.

Abstract: A logic simulation system and method reduces the number of events to be simulated. The simulator receives a user specified circuit netlist denoting a specified logic circuit's components and the nodes interconnecting those components. A user specified watched nodes list identifies the circuit nodes for which output waveforms are to be generated. A cell library provides cell delay data representing signal delays from each input port to each output port of each circuit component. A set of input signal waveforms are compiled into a sequence of variable length time periods and each input signal is assigned an extended boolean value for each time period. The extended boolean values identify signals that are stable over the time period, signals with a single transition during the time period, and signals with multiple transitions during the time period.

Abstract: A device for simultaneous data input and output and program execution support in digital processors is disclosed. The device includes a plurality of controllable input and output ports for inputting and outputting data from the device, a data cache memory which is selectively couplable to each of the plurality of input and output ports, and a controller for controlling the plurality of input and output ports and the data cache memory. The connectivity and controlablity provided by the present invention effectuates a transfer of data between any of the plurality of input and output ports or the data cache memory. The device provides multiport high-speed and high-throughput non-multiplexed data input and output while maintaining the speed and throughput characteristics of the digital processor because the input/output data transfer takes place simultaneously with digital processor program execution. The processor need not wait for data transfers from external data sources when this device is used.

Abstract: A device for multi-precision and block arithmetic support in a digital processor including a multiplier for multiplying two signed, unsigned or signed and unsigned binary numbers and having a dynamic range greater than -1 to +1, an arithmetic and logic unit for performing arithmetic and logic operations, a barrel shifter for barrel shifting at least one binary number, shifters for selectively shifting the output of the multiplier and multiplexers for selecting and interconnecting the outputs and inputs of the multiplier, the arithmetic and logic unit, the barrel shifter and the shifters.