Patents Assigned to Hitachi Microcomputer
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Patent number: 6647509Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.Type: GrantFiled: December 24, 2002Date of Patent: November 11, 2003Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.Inventors: Shinya Ichinohe, Norihide Noyama, Tokuhiro Niwa, Masao Nakamura
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Patent number: 6642083Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.Type: GrantFiled: January 30, 2002Date of Patent: November 4, 2003Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems, Ltd., Hitachi ULSI Engineering Corp.Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
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Patent number: 6583049Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.Type: GrantFiled: December 3, 2001Date of Patent: June 24, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Microcomputer System Ltd.Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
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Patent number: 6538329Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.Type: GrantFiled: August 21, 2001Date of Patent: March 25, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Microcomputer System Ltd.Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
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Patent number: 6505311Abstract: A network system has a plurality of networks. A first internetwork apparatus has a plurality of first ports each connected to the plurality of networks and a second internetwork apparatus has a plurality of second ports each connected to the plurality of networks. A data transmission path is connected to the first and second internetwork apparatuses to transmit data therebetween. In the normal state, each of the plurality of first ports is able to transmit and receive data to and from one of the plurality of networks while the plurality of second ports are able to transmit, but not receive data from the plurality of networks. A failure occurring in one of the plurality of first ports and a route therefrom to one of the plurality of networks is detected.Type: GrantFiled: October 3, 2000Date of Patent: January 7, 2003Assignees: Hitachi, Ltd., Hitachi Microcomputer SystemInventors: Shinya Ichinohe, Norihide Noyama, Tokuhiro Niwa, Masao Nakamura
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Patent number: 6476467Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.Type: GrantFiled: June 1, 2001Date of Patent: November 5, 2002Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems Ltd.Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
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Patent number: 6343357Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: August 3, 2000Date of Patent: January 29, 2002Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6300237Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminium film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.Type: GrantFiled: February 8, 1999Date of Patent: October 9, 2001Assignees: Hitachi Ltd., Hitachi ULSI Engineering Corp., Hitachi Microcomputer System Ltd.Inventors: Masayuki Suzuki, Shinji Nishihara, Masashi Sahara, Shinichi Ishida, Hiromi Abe, Sonoko Tohda, Hiroyuki Uchiyama, Hideaki Tsugane, Yoshiaki Yoshiura
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Patent number: 6278176Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.Type: GrantFiled: April 7, 2000Date of Patent: August 21, 2001Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
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Patent number: 6272620Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: April 4, 2000Date of Patent: August 7, 2001Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6253308Abstract: A microcomputer CMU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: April 2, 1998Date of Patent: June 26, 2001Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6249532Abstract: A billing system for use in a chargeable program broadcasting is capable of reliably billing a subscriber for program reception while preventing unauthorized reception thereof. A receiving terminal includes a primary terminal 100 and a secondary terminal 150. The primary terminal 100 receives a compressed video signal and confirms by an error checker 113 thereof whether there is a transmission error and bills, by a billing device 114 thereof, the receiving subscriber on the basis of an error information and a program information, etc., separated from the video signal by a separation circuit 112. The compressed video data is time-axis multiplexed with a terminal identifying code and a key signal and transmitted to the secondary terminal 150. In the secondary terminal 150, a bill for the subscriber is confirmed by the terminal identifying code and the compressed data is decoded by a decoder circuit 166 thereof.Type: GrantFiled: January 26, 1999Date of Patent: June 19, 2001Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems, Ltd.Inventors: Kazuhiko Yoshikawa, Hitoaki Owashi, Hiroyuki Hayakawa, Tadasu Otsubo, Kyoichi Hosokawa
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Patent number: 6182742Abstract: A cooling apparatus for use with an electronic system provides an uninterrupted operation capability. A pump supplies a cooling liquid to a liquid-cooled electronic system. The pump is controlled by a controller that also controls a three way valve for controlling the operation of a three-way valve for regulating the flow quantity of the cooling liquid flowing into a heat exchanger for cooling the cooling liquid. The cooling apparatus has a plurality of cooling control units. While one cooling control unit is in operation, the other is in the standby state. If one cooling control unit fails, the standby cooling control unit is automatically put in the operating state, thereby allowing servicing of the failing unit without interrupting the operation of the liquid-cooled electronic system and the cooling apparatus.Type: GrantFiled: June 19, 1997Date of Patent: February 6, 2001Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems Ltd.Inventors: Tatsuya Takahashi, Shizuo Zushi, Tetsuo Ogata
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Patent number: 6148411Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.Type: GrantFiled: August 26, 1999Date of Patent: November 14, 2000Assignees: Hitachi, Ltd., Hitachi Microcomputer System, Ltd.Inventors: Shinya Ichinohe, Norihide Noyama, Tokuhiro Niwa, Masao Nakamura
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Patent number: 6131154Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: July 23, 1997Date of Patent: October 10, 2000Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System, Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6112174Abstract: A speech recognition system realizing large-vocabulary speech recognition at a low cost without deteriorating the rate of recognition and a recognition speed performance is provided with a dictionary change-over section for making a change-over between dictionaries to be subjected to speech recognition in accordance with dictionary change-over information, a first memory for storing a plurality of dictionaries, a second memory for storing one dictionary made an object of recognition, and a speech recognition section for performing a speech recognition processing, whereby speech recognition is performed while making a change-over between dictionaries, as required. For example, in a car navigation speech recognition system, the change-over between dictionaries is made for each area in accordance with position information.Type: GrantFiled: November 13, 1997Date of Patent: August 29, 2000Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.Inventors: Shinji Wakisaka, Kazuyoshi Ishiwatari, Kouji Ito, Tetsuji Toge, Makoto Tanaka
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Patent number: 6060770Abstract: The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.Type: GrantFiled: January 14, 1998Date of Patent: May 9, 2000Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.Inventors: Hisao Nakamura, Seiichi Ichihara, Ryosuke Kimoto, Hiroshi Kawakubo, Ryo Haruta, Hiroshi Koyama
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Patent number: 6046770Abstract: Smooth interlocking operation of an optical zooming device and an electronic zooming device are realized by storing an amount of mechanical play of the optical zooming device in a play memory and then calculating the amount of mechanical play of the optical zooming from both the stored amount of mechanical play and lens drive control information to change the interlocking operation starting point of the optical zooming device and the electronic zooming device.Type: GrantFiled: March 10, 1997Date of Patent: April 4, 2000Assignees: Hitachi, Ltd., Hitachi Microcomputer Systems Ltd.Inventors: Kazunori Uemura, Takashi Takahashi
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Patent number: 6032266Abstract: A network system includes a plurality of networks, a first internetwork apparatus having a plurality of first ports each connected to the plurality of networks, a second internetwork apparatus having a plurality of second ports each connected to the plurality of networks, and a data transmission path connected to the first and second internetwork apparatuses to transmit data mutually between the first and second internetwork apparatuses. In the normal state, each of the plurality of first ports is caused to be able to transmit and receive data to and from one of the plurality of networks and the plurality of second ports are caused not to be able to receive data from the plurality of networks and to be able to transmit data to the plurality of networks.Type: GrantFiled: April 3, 1997Date of Patent: February 29, 2000Assignees: Hitachi, Ltd., Hitachi Microcomputer System, Ltd.Inventors: Shinya Ichinohe, Norihide Noyama, Tokuhiro Niwa, Masao Nakamura
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Patent number: 5991545Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: June 7, 1995Date of Patent: November 23, 1999Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp., Hitachi Microcomputer System Ltd.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe