Abstract: In a buffer memory, a validity flag to be added to each data portion is stored in a tag array or address section at a location corresponding to each data portion. After determining whether each validity flag is to be used as a search object, based upon the data portion to be accessed during searching the tag array and an access mode, the address and its validity flag are simultaneously searched. The logical sum of each output of the search result on a word coincidence line becomes a hit judgement signal.

Abstract: In a network system wherein a plurality of terminal devices communicates with each other via respective node devices over a ring transmission line, a transmitting node device can confirm whether a multicast information transmission has succeeded or failed. The transmitting node device send a response frame after a multicast information frame. A receiving node device relays the multicast information frame and a response frame from the upstream node device to the downstream one when the multicast information has been received successfully, or in case of a failure in receiving the multicast information, sends a response frame to the downstream node device by changing at least part of the response frame from the upstream node device. The transmitting node device can determine from a received response frame if there is one or more of the receiving node devices which cannot receive the multicast information.

Abstract: In a MOS static RAM, data lines disposed in a memory array and common data lines to be coupled with the data lines through a data line selection circuit are supplied with bias voltages of a level lower than a power source voltage level through bias MOSFETs. Normally, where the stand-by period of the RAM is long, the bias voltages of the data lines and the common data lines are abnormally raised by the leakage currents or tailing currents of the bias MOSFETs. As a result, the data read-out speed of the RAM is lowered. Such abnormal potential increases of the data lines and the common data lines are prevented by connecting resistance elements of comparatively high resistances (such as made of polycrystalline silicon layers), between the respective data lines and common data lines and the ground point of the circuitry.