Abstract: In a voltage converter which is disposed in a semiconductor integrated circuit so as to lower an external supply voltage and to feed the lowered voltage to a partial circuit of the integrated circuit; the voltage converter is constructed so as to produce an output voltage suited to an ordinary operation in the ordinary operation state of the semiconductor integrated circuit and an aging voltage in the aging test of the circuit.

Abstract: An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provided which is capable of supplying selectively a signal, input to the internal bus, to a specified functional module in place of an individual signal.

Abstract: In a voltage converter which is disposed in a semiconductor integrated circuit so as to lower an external supply voltage and to feed the lowered voltage to a partial circuit of the integrated circuit; the voltage converter is constructed so as to produce an output voltage suited to an ordinary operation in the ordinary operation state of the semiconductor integrated circuit and an aging voltage in the aging test of the circuit.

Abstract: An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

Abstract: A microcomputer includes one or more registers therein. These registers are provided for defining a specific address area. When a processor unit in the microcomputer accesses an address in the specific address area, it acknowledges the access to change the bus width and/or bus cycle of the microcomputer dynamically.

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

Abstract: In a one-chip microcomputer, an electrically programmable read only memory (EPROM) is formed together with a read-only memory (ROM) and random access memory (RAM) on one semiconductor substrate. Data such as fixed data necessary in the microcomputer can be changed by the use of the EPROM. In case data are to be written in the EPROM, an EPROM writer is used. This EPROM writer outputs write data to the EPROM and checks (or verifies) the data written in the EPROM immediately thereafter. If any error is detected, a subsequent data write is interrupted. In order to inhibit the unnecessary operation interruption in case the address designated by the EPROM writer comes out of the range of the EPROM, a checking (or verifying) data signal to be fed from the one-chip microcomputer to the EPROM writer is forcibly set at a level which indicates satisfactory operation of the EPROM.

Abstract: A microprocessor including instruction decoding apparatus, instruction execution apparatus and information holding apparatus. The microprocessor performs a first step of storing information specifying the kind of operation to be performed by the instruction execution apparatus, upon execution of a first instruction, in the information holding apparatus and a second step of causing the instruction execution apparatus to perform the kind of operation specified by information stored in the information holding apparatus when a second instruction is decoded and includes information specifying that the operation to be performed by the instruction execution apparatus is the kind of operation specified by the information stored in the information holding apparatus.

Abstract: The semiconductor integrated circuit device formed on one semiconductor substrate employs a plurality of first and second circuit blocks constituting functions of the same kind. The first and second circuit blocks, however, are implemented with respectively different types of circuits. The type of circuit employed in the respective first and second circuit blocks is necessarily consistent with the particular operation speed requirements thereof, such as, in connection with high-speed and low-speed circuit requirements for writing into the memory of a display system.

Abstract: An information life cycle management system and an information organizing method using the computer system stores information objects composed of a database and program, and a data processing device for processing an information object which is a block of the information in the storage device. Processing and execution of an information object is managed based on information life cycle states, starting with generation of the information object and ending with aborting the information object. An information accessor manager governs the available operation type and area of use of manager information based on the information life cycle state. As information object definition language defines attributes of the information structure and information life cycle state and the managed information object. The information objection is managed in accordance with contents defined by the language.

Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Abstract: A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and corresponding operand data. A selector chooses whether a logical operand address or logical instruction address should access the respective cache memory or the main memory to obtain an instruction or operand data. Furthermore, the processor includes the capability of invalidating all of the data in either the instruction cache memory or operand cache memory based on a software instruction signal received at a purge unit.

Abstract: A microcomputer includes one or more registers therein. These registers are provided for defining a specific address area. When a processor unit in the microcomputer accesses an address in the specific address area, it acknowledges the access to change the bus width and/or bus cycle of the microcomputer dynamically.

Abstract: In a video signal apparatus, a carrier signal generating circuit includes a VCO for generating a signal having a frequency at least twice that of a carrier signal necessary for conversion to a lower band with a sub-carrier in an NTSC system, a one-half divider circuit for dividing the VCO frequency signal by two, a delayed flip-flop circuit for receiving the divided signal and the sub-carrier signal to generate a difference frequency signal, a 1/40 divider circuit for dividing the Q output, a phase comparator circuit for comparing the phases of the 1/40 divided signal and the horizontal synchronizing signal to output a phase difference, a frequency discriminator circuit for comparing the phase of the flip-flop output with the frequency-divided output of the horizontal synchronizing signal to output a frequency error, and a circuit for converting the output of the phase comparator circuit and the frequency error into DC voltages and applying their sum as a control voltage for the VCO.

Abstract: A method and apparatus for relocating a storage such that a physical address area of the storage, which is allocated to an absolute address area, is replaced with a new physical address area. This relocation process is performed with a Floating Address Register for translating an absolute address into a physical address in a hierarchy storage system including a main storage and a store-in cache memory, thereby reducing a stopping time of the main storage during the relocation process. According to the method, data of the area of object physical addresses to be relocated is fetched into a block of the cache memory, and then the new physical addresses of the storage are allocated to the absolute address to which the old physical addresses have been allocated.

Abstract: A problem solving system including apparatus for representing a relationship between a goal including subgoals and its lower level subgoals and for achieving the goal as a strategy of a first kind. Apparatus is provided for repetitively dividing a goal including subgoals into its lower level subgoals according to the relationship between the goal and the subgoals. A strategy of a second kind is used to specify the functions to be performed by the apparatus to achieve the lowest subgoal. Apparatus is also provided for simplifying and solving a complicated problem by executing the goal including subgoals by use of the strategies of the first and second kinds.

Abstract: When a current that flows into a power output element is greater than a predetermined value, pulse width-modulated signals are formed which vary in inverse proportion to the current value in order to drive the power output element. When an excess current flows into the power output element, therefore, the power output element is allowed to intermittently operate for only short periods of time, and the current can be decreased during the current-limiting operation.

Abstract: A method for evaluating the life of a connection between members including the steps of extracting parameters defining the shearing strain of a predetermined model representing the connection thereby to calculate the values of plural shearing strains of the connection, calculating the equivalent strain amplitude corresponding to thermal fatigue stress for each of the values of the plural shearing strains defining the relationship between the shearing strain and the equivalent strain amplitude, formulating a life evaluation criterion equation expressed using the equivalent strain amplitude, calculating, for the connection, the equivalent strain amplitude corresponding to each of the shearing strains actually measured using the equation, and substituting the equivalent strain amplitude for the life evaluation criterion equation to acquire the life of the connection.

Abstract: Task execution control for a multiprocessor wherein at a time point when a post issue task ends the use of a shared resource, the shared resource is released, another task which is running on another processor is allowed to lock the shared resource, and thereafter the task is made ready. After that, the post procedure is initiated, and thereafter through the high-speed dispatch procedure, the processor is granted first to a task which has failed to lock the shared resource, and the task is prompted to retry to lock the shared resource.