Abstract: A data name standardizing/unifying system for standardizing the names of data belonging to data items having different names and transferred or compared among data files so as to be unified for programs. For standardizing the data names, names of data items assumed to have same contents are gathered and a table indicating data names to be replaced are generated to be displayed together with prompting for entry of the standard data name to replace. From this table, standardization for data names is accomplished by this replacement of the data name in the programs. For identifying the standardized data names created for the different files, different file names or different and upper file names are added to a division of program which refers to the files.

Abstract: A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

Abstract: In a data processing system having a central processing unit, at least an input/output unit such as an MT unit or a floppy disk unit, a memory, an address bus, a first address translation unit, a second address translation unit, and an address selection unit, an output address from the central processing unit is translated by the first address translation unit to supply a resultant address to the address bus and, an output address from the input/output unit is directly fed to the address bus. An address on the address bus is delivered to the address selection unit, and the address selection unit selectively supplies the memory with the output address delivered from the first translation unit onto the address bus or with the resultant address obtained by translating the output address from the input/output unit by means of the second translation unit.