Abstract: When cooling power corresponding to an amount of heat generated by an electronic apparatus can be generated by either n or n+1 cooling units, n+1 cooling units are operated such that each of the cooling units keeps a sufficient margin in reserve. In this manner, even if an abnormality occurs in one of the cooling units, the operation can be continued by the n cooling units. Further, since an operation frequency of a compressor in the cooling unit can be decreased to rotate a motor in the compressor at a lower rotational speed, a speed at which a bearing is worn is slowed, whereby the useful life of the bearing can be prolonged.

Abstract: In a communications system having a plurality of stations interconnected by a two-line circuit, in which the two-line circuit consists of a data bus circuit for transmitting a series of data bits between at least one sending station and at least one receiving station of the plurality of stations and a clock bus circuit for transmitting clock signals in synchronism with each of the data bits; the data bus circuit sends a signal or a command requesting the receiving station to enter a standby or an execute state after taking in data supplied, while a logic value on the clock bus circuit is fixed. In more detail, the sending station transmits signals to make at least one of the receiving stations enter the standby state after taking in data and then sends data to another receiving station, after which the sending station sends a signal or command to make both the first and second receiving stations simultaneously enter the execute state.

Abstract: A data processing system capable of searching for desired data requested by a computer from a memory unit. To obviate a disadvantage that the computer has read data partially including desired data from the memory unit and selected the desired data from the read data, the data processing system is provided with a data processing unit connected to a control unit for controlling a memory unit. Desired data is selected by this data processing unit.

Abstract: An object-oriented data base management system connected to a plurality of data bases includes a class definition unit, a static inheritance processing unit included within the class definition unit, a message processing unit, a dynamic inheritance processing unit included within the message processing unit, and an object management unit. The object-oriented data base management system is of the type that defines the inheritance relationship between a plurality of classes and an arbitrary class and the inheritance priority order, the class being a basic unit of programming, and executes the data processing by solving the inheritance relationship between classes in accordance with the priority order. There is prepared, for each class, updatable inheritance solution status information which the static inheritance processing unit causes to be stored in a table. The inheritance solution status information includes status information and time information.

Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.

Abstract: In a system for data processing by use of a processing language controlled by a job control program for coupling a file having at least one data item to a data set, a method of standardizing data items in an existing program stored in a storage and having a procedure part and a data definition part is disclosed. The names of two data items including the source and destination items of moving in the transfer designated in a plurality of data transfer instructions in an existing program are stored in the storage, and the equivalence number attached to the name of the transfer source item of each of the plurality of data transfer instructions is attached to the name of the transfer destination item. If a plurality of files assigned in the data definition part are defined in a single data set, the file equivalence number is attached to the plurality of files in the storage.

Abstract: The computer aided planning support system of this invention is constructed of a planning information input device from which an object data for making a plan is inputted; an object data storage unit for storing the inputted object data; a planning unit for making a plan by reading the object data stored in the object data storage unit and processing the read-out data in accordance with a planning program; a planning data storage unit for storing the data associated with the plan made by the planning unit; a planning data processing unit for processing the planning data stored in the planning data storage unit in accordance with a predetermined scheduling function and sending the processed data to the planning unit; and a planning information output device for outputting the planning result generated by the planning unit in the form a user can use it.

Abstract: When a semiconductor integrated circuit device having a wiring structure of three or more layers is hierarchically considered as a collection of a plurality of functional blocks, each functional block is internally connected by wirings in the first wiring layer, in which wirings have their main extended direction prescribed to be the X-direction, and wirings in the second wiring layer, in which wirings have their main extended direction prescribed to be the Y-direction, formed over the first wiring layer. Wirings in the third wiring layer, in which wirings have their main extended direction prescribed to be the same as the wirings in the second wiring layer, formed over the second wiring layer, together with wirings in the first and second wiring layer, are used as signal wirings between functional blocks, while the wirings in the third wiring layer are used as power supply wirings for providing power supply to functional blocks.

Abstract: A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.

Abstract: In a method for determining an optimum scheduling in a computer-aided scheduling system the data associated with a schedule to be generated is previously stored in a memory data. A strategy decision table showing therein one or more scheduling strategies suitable for a plurality of the states in a scheduling process is prepared. An optimization definition table indicating degree of improvement precedence or precedence order of the scheduling strategies of the evaluation items, where degree of improvement precedence is defined as degree of improvement of evaluation value of he evaluation item in changing of the scheduled strategy, is prepared. A schedule is generated by repetition of selecting and executing the scheduling strategies by using the strategy decision table. The other schedules are generated by changing the scheduling strategy selected in the state of the scheduling process by using the optimization definition table. An optimum schedule having the best evaluation value is selected.

Abstract: A semiconductor gate array device compatible with ECL and/or TTL, wherein the input buffer unit includes a TTL input stage, an ECL input stage and a common output stage, and the output buffer unit includes a common input stage, an ECL output stage and a TTL output stage. When the device is to be used as a TTL input interface, the TTL input stage and the common output stage are coupled together and when the device is to be used as an ECL input interface, the ECL input stage and the common output stage are coupled together. When used as a TTL output interface, the common input stage and the TTL output stage are coupled together and when used as an ECL output interface, the common input stage and the ECL output stage are coupled together. Therefore, the input/output interfaces exhibit general applicability to meet the user's demands, yet enabling the layout areas of the input and output buffer portions to be decreased.

Abstract: A power supply device has its power supply conductor bars, in which a.c. currents caused by a.c. noises flow in the same direction, laid closely in parallel while retaining their insulation thereby to increase the total inductance so that the impedance increases without accompanied by an increase in the d.c. resistance of the power supply conductor bars. An increased coupling impedance of the power supply conductor bars effectively attenuates the a.c. noises from d.c. power units, which then supply d.c. power with reduced a.c. noises to an electronic apparatus such as a computer through the power supply device.