Abstract: The execution of an instruction for one of co-processors is subrogated by information processing function implemented in the host-processor. When a co-processor identification code involved in the instruction for the co-processor agrees with a host-processor internal processing identification code set in the host-processor, the instruction decoder of the host-processor starts the information subrogating processing function. Thus, protocol control for communication from the host-processor to co-processors can be omitted so that a high-speed data processing becomes possible.