Patents Assigned to Hitachi Ome Electronic Co., Ltd.
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Patent number: 4598197Abstract: A projection aligner wherein light from a light source is passed through a mask so as to focus an image of a pattern of the mask on a wafer, characterized in that at least one sensor for monitoring a luminosity and a distribution thereof is disposed in an optical path between the light source and the mask, whereby a luminosity and a distribution thereof on the wafer can be controlled to proper values. The projection aligner is effective for application to minute processing technologies for the production of semiconductor devices, etc.Type: GrantFiled: August 2, 1983Date of Patent: July 1, 1986Assignees: Hitachi, Ltd., Hitachi Ome Electronic Co., Ltd.Inventors: Koyo Morita, Keizo Nomura, Hiroshi Nishizuka, Tai Hoshi, Yoichiro Tamiya, Terushige Asakawa
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Patent number: 4485957Abstract: A wire bonder is frequently used for assembling the electronic parts of a semiconductor device or the like and exhibits an effect in the electric connections of the aforementioned electronic parts with a fine metal wire. The wire bonder according to the present invention comprises a clamper for clamping a bonding wire, and bonding wire disconnection detecting means for detecting the disconnection of the bonding wire in terms of the wire clamping state of the clamper. In order to detect highly accurately and reliably the disconnection of the bonding wire, the aforementioned bonding wire disconnection detecting means is characterized by the provision of a detecting unit for detecting a quantity which corresponds to the facing gap of the clamper during the clamping operation.Type: GrantFiled: May 26, 1982Date of Patent: December 4, 1984Assignees: Hitachi, Ltd., Hitachi Ome Electronic Co., Ltd.Inventors: Tatsuo Sugimoto, Seiji Shigyo, Kazutoshi Takashima, Yuichi Komaba
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Patent number: 4366397Abstract: The collectors of differential pair transistors having their emitters connected to each other are connected to a positive power source voltage via respective load resistors. The emitters are connected to a negative power source voltage via a current source transistor.The base bias voltage of the current source transistor is supplied from a bias circuit operating on the difference voltage between the positive power source voltage and the negative power source voltage.When the positive power source voltage drops, the base bias voltage of the current source transistor drops in response thereto. Hence, the value of a current flowing through the current source transistor decreases. Due to this decrease of the current, the voltage drop of the load resistors decreases, thereby off-setting a low level potential of the collector output signals of the differential pair transistors.Thus, the differential pair transistors are prevented from being driven into saturation.Type: GrantFiled: June 9, 1980Date of Patent: December 28, 1982Assignees: Hitachi, Ltd., Hitachi Ome Electronic Co., Ltd.Inventors: Nobuaki Kitamura, Kouji Masuda, Masao Mizukami
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Patent number: 4336504Abstract: A push-pull output circuit which is capable of producing a relatively-high maximum output voltage without the use of a bootstrap capacitor provides positive and negative half cycle output circuits which are constructed as inverted Darlington output circuits to which current mirror circuits and level shifting elements are coupled. As a result, the distortion factor of an open loop characteristic in the push-pull output circuit is improved.Type: GrantFiled: April 21, 1980Date of Patent: June 22, 1982Assignees: Hitachi, Ltd., Hitachi Ome Electronic Co., Ltd.Inventors: Kunio Seki, Norihisa Katoh
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Patent number: 4300213Abstract: Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.Type: GrantFiled: October 31, 1979Date of Patent: November 10, 1981Assignees: Hitachi, Ltd., Hitachi Ome Electronic Co., Ltd.Inventors: Nobuyoshi Tanimura, Hiroshi Fukuta, Kotaro Nishimura, Tokumasa Yasui
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Patent number: 4290119Abstract: A memory circuit includes memory cells and access circuit for accessing to desired memory cells. The access circuit is driven by a driver which includes an emitter coupled logic for providing a switch-on signal of a low level in response to an input signal. A switch circuit in the driver provides the access circuit with a drive signal of a low level in response to the switch on signal. The driver further includes a control circuit for clamping the output of the emitter coupled logic to a non-drive signal of a high level when supply voltages does not satisfy predetermined conditions.Type: GrantFiled: February 7, 1980Date of Patent: September 15, 1981Assignees: Hitachi, Ltd., Hitachi Ome Electronic Co., Ltd.Inventors: Kouji Masuda, Masao Mizukami, Nobuaki Kitamura