Abstract: A disk array controller connected in a star configuration with a plurality of interfaces each having a processor, a shared memory connected to the interfaces by access paths and a common bus connected to the interfaces. The shared memory transmits interruption signals to the interface by way of control signals when one of the processors writes broadcast data into the shared memory.
Type:
Grant
Filed:
March 13, 2000
Date of Patent:
May 13, 2003
Assignees:
Hitachi, Ltd., Hitachi Software Engineering Ci., Ltd., Hitachi Video and Information System, Inc.