Patents Assigned to Hitachi ULSI
  • Publication number: 20140225189
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Application
    Filed: April 23, 2014
    Publication date: August 14, 2014
    Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Sumito NUMAZAWA, Yoshito NAKAZAWA, Masayoshi KOBAYASHI, Satoshi KUDO, Yasuo IMAI, Sakae KUBO, Takashi SHIGEMATSU, Akihiro OHNISHI, Kozo UESAWA, Kentaro OISHI
  • Publication number: 20140198577
    Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.
    Type: Application
    Filed: March 16, 2014
    Publication date: July 17, 2014
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiro TANAKA, Yukiko UMEMOTO, Mitsuru HIRAKI, Yutaka SHINAGAWA, Masamichi FUJITO, Kazufumi SUZUKAWA, Hiroyuki TANIKAWA, Takashi YAMAKI, Yoshiaki KAMIGAKI, Shinichi MINAMI, Kozo KATAYAMA, Nozomu MATSUZAKI
  • Publication number: 20140159245
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicants: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Taku KANAOKA, Masashi SAHARA, Yoshio FUKAYAMA, Yutaro EBATA, Kazuhisa HIGUCHI, Koji FUJISHIMA
  • Patent number: 8748266
    Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: June 10, 2014
    Assignees: Renesas Electronics Corporation, Hitachi Ulsi Systems Co., Ltd.
    Inventors: Sumito Numazawa, Yoshito Nakazawa, Masayoshi Kobayashi, Satoshi Kudo, Yasuo Imai, Sakae Kubo, Takashi Shigematsu, Akihiro Ohnishi, Kozo Uesawa, Kentaro Oishi
  • Publication number: 20140145259
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi INAGAWA, Nobuo MACHIDA, Kentaro OOISHI
  • Patent number: 8704291
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: April 22, 2014
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Patent number: 8698224
    Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.
    Type: Grant
    Filed: April 20, 2013
    Date of Patent: April 15, 2014
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
  • Publication number: 20140099770
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: December 9, 2013
    Publication date: April 10, 2014
    Applicants: Hitachi ULSI Systems Co., Ltd., Renesas Electronics Corporation
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 8674745
    Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: March 18, 2014
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuo Tanaka, Hiroyuki Mizuno, Rie Nishiyama, Manabu Miyamoto
  • Patent number: 8669659
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: March 11, 2014
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Patent number: 8604505
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: December 10, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 8605478
    Abstract: In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: December 10, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroyuki Mizuno, Takeshi Sakata, Nobuhiro Oodaira, Takao Watanabe, Yusuke Kanno
  • Publication number: 20130241029
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: April 8, 2013
    Publication date: September 19, 2013
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi KURODA, Kozo WATANABE, Hirohiko YAMAMOTO
  • Publication number: 20130235668
    Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.
    Type: Application
    Filed: April 20, 2013
    Publication date: September 12, 2013
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiro TANAKA, Yukiko UMEMOTO, Mitsuru HIRAKI, Yutaka SHINAGAWA, Masamichi FUJITO, Kazufumi SUZUKAWA, Hiroyuki TANIKAWA, Takashi YAMAKI, Yoshiaki KAMIGAKI, Shinichi MINAMI, Kozo KATAYAMA, Nozomu MATSUZAKI
  • Publication number: 20130229144
    Abstract: A secondary-battery monitoring device capable of realizing highly reliable overcurrent detection and a battery pack having it are provided. When an overcurrent flowing to a secondary battery is to be detected by utilizing a current detection voltage generated via on-resistance of a discharge-control switch and a charge-control switch, a voltage correction circuit that generates a correction voltage having a characteristic varied by positive slope or negative slope along with increase in a power supply voltage is provided, and the correction voltage is added to the detection voltage or a reference power supply voltage with the polarity that cancels out the slope of voltage variation caused in the detection voltage, and then the voltage is input to a comparator circuit. In this manner, variation in the overcurrent determination current is reduced.
    Type: Application
    Filed: February 2, 2013
    Publication date: September 5, 2013
    Applicant: HITACHI ULSI SYSTEMS CO., LTD.
    Inventors: Shogo Nagata, Yasuaki So, Takeshi Yamaguchi, Norihito Kawaguchi
  • Patent number: 8504762
    Abstract: A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read operations is provided including a nonvolatile memory; a volatile memory for storing file management information of the nonvolatile memory; a controller for controlling the nonvolatile memory and the volatile memory; and a power supply maintaining unit for supplying power to the nonvolatile memory, the volatile memory, or the controller upon power shutdown. The controller reads the file management information in the nonvolatile memory upon power-on and writes the same in the volatile memory, and read and write operations are performed based on the file management information in the volatile memory, and the file management information in the volatile memory is written in the nonvolatile memory upon power shutdown.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: August 6, 2013
    Assignee: Hitachi ULSI Systems Co., Ltd.
    Inventors: Masahiro Matsumoto, Takayuki Okinaga, Shuichiro Azuma, Shigeru Takemura, Yasuyuki Koike, Kazuki Makuni
  • Publication number: 20130187610
    Abstract: A charging/discharging monitoring device of a battery pack, includes: a plurality of monitoring integrated circuits; a plurality of wiring boards on which the plurality of monitoring integrated circuits are mounted, respectively; and a plurality of signal transmission paths for, via corresponded respective capacitors, connecting between the plurality of wiring boards. The charging/discharging monitoring device is configured with a two-wire transmission path for connecting between terminals of an upstream-side monitoring integrated circuit of daisy chain connection and a downstream-side monitoring integrated circuit thereof, and a wire length of a wiring part which connects between the respective capacitors and terminals of the corresponding monitoring integrated circuits on the wiring boards is a length in which resonance is not caused by the electromagnetic wave noises in an electromagnetic wave noise environment under which the wiring boards are arranged.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 25, 2013
    Applicant: HITACHI ULSI SYSTEMS CO., LTD.
    Inventor: HITACHI ULSI SYSTEMS CO., LTD.
  • Patent number: 8476138
    Abstract: Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 2, 2013
    Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Electronics Corporation
    Inventors: Hiraku Chakihara, Kousuke Okuyama, Masahiro Moniwa, Makoto Mizuno, Keiji Okamoto, Mitsuhiro Noguchi, Tadanori Yoshida, Yasuhiko Takahshi, Akio Nishida
  • Publication number: 20130145084
    Abstract: An electronic apparatus provided with a serial communication circuit achieving a baud rate adjustment with high precision is provided. For example, a bit width of each of a plurality of bits in received serial data is measured by a clock counter, and an average value of the bit width is calculated detecting its maximum value and minimum value. Moreover, for example, a maximum tolerance and a minimum tolerance are calculated as a value substantially 1.5 times the average value and a value substantially 0.5 times the average value, and determination is made as to whether or not the maximum value and the minimum value are within a range between the maximum tolerance and the minimum tolerance. If they are within the range, the corresponding average value is set in a baud rate setting register.
    Type: Application
    Filed: December 3, 2012
    Publication date: June 6, 2013
    Applicant: Hitachi ULSI Systems Co., Ltd.
    Inventor: Hitachi ULSI Systems Co., Ltd.
  • Patent number: 8426969
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 23, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto