Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.

Abstract: In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store multivalued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the erase level, and data is successively written into memory cells whose threshold voltages are higher.

Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.

Abstract: A data processor includes a register group having registers of the number larger than the number of registers which can be designated by a register specifier field of an instruction. The register group consists of a plurality of register queues with respect to logical register numbers designated in the instruction, each register queue including a plurality of physical registers. In the data processor, a physical register number forming section is provided for converting the logical register number to a physical register number in the register queue corresponding to the logical register number, by using queue control information designated in the register specifier field and read/write information decided by the kind of the instruction and the position of the register specifier field in the instruction.

Abstract: A non-volatile memory, such as a flash memory card, using a rewritable non-volatile memory is provided with an improved write-protect arrangement. The non-volatile memory includes a collectively electrically erasable and writable memory (e.g., a flash memory), a reset IC for generating a power-on reset signal upon turn-on of the power supply, and a card controller for performing control between each flash memory device and a memory card interface. The flash memory is set with a write protect save register written with an address of an area desired to be subjected to write protect, the write protect save register belonging to an attribute area, and a protect range is set from the system. Since the address to be write-protected is itself written in the non-volatile flash memory, the address will continue to be stored, even if the power is turned off. A method for software write protection control is also provided.

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.

Abstract: An AAL1 processing method in a cell disassembly apparatus for performing pointer comparison processing on the assumption that a pointer is inserted in each ATM cell, in parallel with sequence number processing, to determine the validity of the result of the pointer comparison processing to control an output data stream. In this case, data associated with each connection required for each processing is read from a memory table based on connection information added to a received ATM cell each time the ATM cell is received, and set in corresponding processing units.

Abstract: A semiconductor memory device is provided which is able to supply data at high speed to a microprocessor (MPU) without being affected by the dispersion of power supply voltage, temperature and production process conditions. A semiconductor chip includes an address buffer, a decoder, a word driver, data lines, a sense amplifier, a main amplifier, an output buffer, and a PLL to which an external clock is applied. The PLL generates controls signals .PHI..sub.1 through .PHI..sub.7 with their phases shifted in turn, and supplies them to those internal circuits ranging from the address buffer to the output buffer. The PLL can control the phases of these control signals to be constant without being affected by the variations of temperature and power supply voltage. Thus, the internal circuits are precharged or equalized by the control signals, and then operated by the control signals to amplify data signal in turn.

Abstract: A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.

Abstract: A data processing apparatus having a built-in flash memory and being capable of performing a rewriting operation of the built-in flash memory, by use of versatilely used PROM writer, has a CPU, an electrically rewritable nonvolatile flash memory both formed in a single semiconductor substrate, and is operable in a mode in which the built-in flash memory is rewritable in accordance with commands supplied from a PROM writer. The data processing apparatus has a command latch which is externally writable when the above-mentioned operation mode is established, a command analyzer, that is, a command decoder, and a sequence controller for controlling a sequence of a rewriting operation of the flash memory in accordance with the decoded output of the command analyzer. The command analyzer and sequence controller may be realized by the CPU.

Abstract: A semiconductor memory device has memory cells provided at intersections between word line conductors and data line conductors. Each of the memory cells includes a cell selecting transistor and an information storage capacitor. The capacitor in each of the memory cells includes a first capacitor component formed over the control electrode of the transistor and a second capacitor component formed over a word line conductor which is adjacent to a word line conductor integral with the control electrode of the transistor. Each of the first and second capacitor components has a common electrode, a storage electrode and a dielectric film sandwiched therebetween, and the storage electrode is at a level higher than the common electrode in each of said first and second capacitor components. The storage electrodes of the first and second capacitor components are electrically connected with each other and with one of the semiconductor regions of the transistor.

Abstract: A flash A/D converter includes a plurality of master comparators for comparing a plurality of reference voltages and an input analog signal to absorb a current with a constant value from a non-inverted output or inverted output of each master comparator, a plurality of constant current sources, a plurality of load resistors and a plurality of slave comparators for outputting desired digital signals. The constant current value of one of the constant current sources coupled to a signal line coupled to the input of the slave comparator of a lower bit side is set to a value larger than that of one of the constant current sources coupled to a signal line coupled to the input of the slave comparator of a higher bit side. Thereby, it is possible to provide a flash A/D converter which has a low power consumption and a high speed.

Abstract: A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically.

Abstract: A program described by using a graphic representation is edited and a text language type programming language is generated from the edited graphic representation. A data table for managing data to be used in programming, a process management table for managing processes applicable to the data and a program table for storing step information of the program are prepared. By using those data, the data and the processes applicable to the data are displayed and a user selects from those displays to graphically represent the program and store the step information of the program in the program table. The delivery of the data during the process is represented by the designation of the data sharing by ports accompanied with the graphic representation. Finally, the target program is generated from the program table.

Abstract: A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-etching method using a first mask, the upper polycrystalline silicon film is patterned at first so far as to form the clearance of the upper-layer fins with the minimum working size of the memory cells of a DRAM, to form the upper-layer fin. Next, the lower-layer fin is formed by the dry-etching method using a second mask which has a pattern enlarged in self-alignment from the pattern of the first mask, so that it is given a larger horizontal size than that of the upper-layer fin.

Abstract: In an animation generating method wherein a component of an apparatus to be designed is defined by an instance of an object-oriented program and a figure is allocated to said instance on a computer, and further an animation method for varying a representation of said figure in connection with the operation of the instance is interactively generated, a designation is made of either a slot of said instance, or a method argument of a method effected to said instance, and further a designation is made of a figure attribute of a figure to be changed in an animation representation. In response to this, an animation method for changing the figure attribute is automatically generated with refererence to the slot of the instance, or the method argument of the method effected to the instance.

Abstract: In a microcomputer system, an access operation is executed in a pipeline mode via buses to which bus masters are connected, and a control of the pipeline execution is performed by a bus controller. Furthermore, an access for delaying this pipeline operation is carried out by low-level of hierarchical buses connected by a buffer and a low-level bus controller.