Patents Assigned to Hitachi ULSI
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Patent number: 7262083Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.Type: GrantFiled: January 12, 2004Date of Patent: August 28, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
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Patent number: 7254068Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.Type: GrantFiled: March 15, 2006Date of Patent: August 7, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
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Patent number: 7251182Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.Type: GrantFiled: February 15, 2006Date of Patent: July 31, 2007Assignees: Renesas Technology Corp., SuperH, Inc., Renesas Northern Japan Semiconductor, Inc., Hitachi ULSI Systems Co., Ltd.Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
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Patent number: 7247576Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.Type: GrantFiled: October 28, 2005Date of Patent: July 24, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
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Patent number: 7242627Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.Type: GrantFiled: February 28, 2006Date of Patent: July 10, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroyuki Mizuno, Takeshi Sakata, Nobuhiro Oodaira, Takao Watanabe, Yusuke Kanno
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Patent number: 7230649Abstract: An image sensor such as the conventional CMOS image sensor, in which automatic controls including so-called automatic iris control and white balance adjustment for adjusting the sensor sensitivity, namely the charge accumulation time in each pixel, according to the brightness of the image sensing ambience are performed, involves the problem that, when the frame rate of the image sensor is slowed to save power consumption, the operation of the automatic control systems will also become slower and the image quality deteriorates. In the invented image sensor system using a CMOS image sensor, while a CMOS image sensor is operated at the full frame rate all the time, a circuit for processing image signals from the CMOS image sensor is operated at a speed close to that of full frame processing only when the power supply is turned on or when the image sensing ambience varies and switched to a lower frame processing speed when automatic controls, including iris control, have become stabilized.Type: GrantFiled: November 12, 2002Date of Patent: June 12, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Takahashi, Hiroyuki Matsumoto, Teruyuki Odaka, Masashi Nakamura, Koji Shida
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Patent number: 7225372Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.Type: GrantFiled: September 27, 2004Date of Patent: May 29, 2007Assignee: Renesas Technology Corp & Hitachi ULSI Systems Co., Ltd.Inventors: Iwao Suzuki, Shuji Kikuchi, Fumie Kobayashi, Hideyuki Aoki
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Patent number: 7224016Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.Type: GrantFiled: February 13, 2004Date of Patent: May 29, 2007Assignees: Elpida Memory, Inc., Hitachi ULSI Systems, Co., Ltd., Hitachi Ltd.Inventors: Yoshitaka Nakamura, Hidekazu Goto, Isamu Asano, Mitsuhiro Horikawa, Keiji Kuroki, Hiroshi Sakuma, Kenichi Koyanagi, Tsuyoshi Kawagoe
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Patent number: 7222272Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.Type: GrantFiled: May 7, 2003Date of Patent: May 22, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yoshio Takazawa, Toshio Yamada, Kazumasa Yanagisawa, Takashi Hayasaka
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Patent number: 7219272Abstract: A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.Type: GrantFiled: June 14, 2002Date of Patent: May 15, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co. Ltd.Inventors: Kenichi Osada, Koichiro Ishibashi, Yoshikazu Saitou, Masashige Harada, Takehiko Kijima
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Patent number: 7212425Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: September 19, 2005Date of Patent: May 1, 2007Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
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Patent number: 7208999Abstract: The present invention provides a semiconductor integrated circuit device equipped with a negative feedback amplifier circuit or a step-down circuit which realizes stabilization of an output voltage effectively in response to a variation in power supply voltage. A constant current source is used to cause a bias current for setting current consumption to flow in a differential amplifying MOSFET. A capacitor is provided between an external power supply voltage and a predetermined circuit node to thereby detect a reduction in the external power supply voltage. An operating current of the differential amplifying MOSFET is increased through the use of a current flowing in the capacitor due to such an external power variation, thereby executing the operation of stabilizing an output voltage corresponding to the reduction in the external power supply voltage.Type: GrantFiled: February 1, 2006Date of Patent: April 24, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventor: Yoshikazu Saitoh
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Patent number: 7208924Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin.Type: GrantFiled: June 3, 2003Date of Patent: April 24, 2007Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Toyoshima, Masahiko Nishiyama
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Patent number: 7209169Abstract: Turning on and off of the light source illuminating an object to be imaged is judged based on brightness changes in small and large areas set up in the frame and an electric charge storage time for each pixel is set up to be equal to the turning-on-and-off period of the light source or an integral multiple thereof. The charge storage time is changed over responsive to the turning-on-and-off period of the light source or the integral multiple thereof to set up a stored light amount for each pixel stepwise and difference in the stored light amount between steps is interpolated by continuous gain control of read-out signals of pixels.Type: GrantFiled: February 28, 2002Date of Patent: April 24, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroyuki Matsumoto, Takashi Takahashi, Teruaki Odaka, Masashi Nakamura, Koji Shida
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Patent number: 7206233Abstract: A memory system is provided which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: GrantFiled: March 18, 2005Date of Patent: April 17, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
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Patent number: 7201326Abstract: An object of the present invention is to prevent secret information that is being internally processed from being inferred through operational information of a secured device, including the current consumption information. One solution is provided by an information processing device having at least a key generation apparatus that generates key data automatically, an encryption unit that encrypts data with the corresponding key data, a register that stores a plurality of encrypted data items with the corresponding encryption key data items, and an arithmetic unit that performs operations using data expressed with the corresponding encryption key data and new key data as the input, encrypts the operation result with new input key data, and outputs the result, thereby being capable of performing internal processing on an encrypted data expression. Accordingly, only encrypted data is transferred on the internal or external data bus line.Type: GrantFiled: December 29, 2003Date of Patent: April 10, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takashi Endo, Masahiro Kaminaga, Takashi Watanabe, Kunihiko Nakada, Takashi Tsukamoto
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Patent number: 7201581Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secret codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level. Owing to the adoption of a plural-column layout corresponding to a form typified by the zigzag fashion in an array of the connector terminals, a relatively simple structure can be adopted in a card slot.Type: GrantFiled: May 3, 2005Date of Patent: April 10, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hirotaka Nishizawa, Haruji Ishihara, Atsushi Shiraishi, Yosuke Yukawa
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Patent number: 7203081Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.Type: GrantFiled: December 27, 2004Date of Patent: April 10, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Masahiko Nishiyama, Keiichi Higeta, Takashi Koba
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Patent number: 7203101Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.Type: GrantFiled: January 12, 2006Date of Patent: April 10, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
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Patent number: 7200061Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.Type: GrantFiled: November 8, 2002Date of Patent: April 3, 2007Assignees: Hitachi, Ltd., Elpida Memory, Inc., Hitachi ULSI Systems Co., Ltd.Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya