Abstract: In the semiconductor integrated circuit device provided with a plurality of second well regions of the same conductivity type, formed by dividing a first well region provided in the semiconductor substrate by an isolation trench, the isolation trench is substantially linear on the semiconductor substrate surface and the ends reach out of the first well region, however there is no intersection part, namely a corner part T part or cross part in the isolation trench. Therefore, no cavity occurs in the filler in the trench and stress is not concentrated on the intersection part. In addition, defects due to junction leak or mechanical damage do not occur, that is, there is no characteristic deterioration occuring. By providing the second well with memory cell, a semiconductor memory device whose characteristic defect rate and reliability defect rate are remarkably low can be formed.