Abstract: A memory array of a static RAM or the like is divided in a word line extending direction to constitute a plurality of sub memory arrays SM0 to SM7, and array selecting signals for selecting the sub memory arrays and sub word line selecting signals for selecting sub word lines are combined to form word line selecting signals selectively. Main word lines M0000 to M0003 for transmitting those word line signals are arranged in parallel with the sub word lines SW000 to SW255. Sub word line drive circuits SWD000 to SWD255 are also coupled to the individual sub word lines for bringing the corresponding sub word lines selectively into selected states by combining at least 2 bits of the word line selecting signals.

Abstract: The partial differential equations inputted with respect to an unknown quantity A are processed according to the finite element method in which simultaneous first-order equations equivalent to the partial differential equations are obtained, and then a matrix equation equivalent to the simultaneous first-order equations, namely, (k.sub.ij) (a.sub.i)=(d.sub.i) is processed to derive a coefficient {a.sub.j } so as to generate a program which calculates the unknown quantity A. For each group of a plurality of elements, the program calculates a contribution determined by the positions of the nodes associated with the elements with respect to a portion of matrix element group such as k.sub.lm and k.sub.ll and a portion of constant group such as d.sub.l and d.sub.m determined by the numbers assigned to a plurality of nodes contained in the group of a plurality of elements and then generates the final values of the matrix element group {k.sub.ij } and the constant {d.sub.

Abstract: This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter.A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit.A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing.The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly.

Abstract: In accordance with the invention, there are disposed a logical register group and a physical register group. Direct access is made to the logical register group on the basis of a register number designated by an instruction. To make access to the physical register group, there is disposed a circuit which converts the register number designated by the instruction to a physical register number.A plurality of arithmetical or logical operation units (ALUs) are disposed to execute a plurality of instructions in parallel. There is further disposed a circuit which supplies an operand data from the physical register group to each ALU and writes the operation result data of each ALU into the physical register group and into the logical register group.When a write register number designated by a preceding instruction A and a succeeding instruction B has the same value a, mutually different physical register numbers b' and b" are determined with respect to the write register number a for both instructions A and B.

Abstract: A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

Abstract: A semiconductor integrated circuit device has an address decoder which is constructed of a plurality of MOSFETs implemented in a switch tree. The switch tree includes first and second switch tree portions which are controlled `on` and `off` by the same input signals. A first switch branch in the first switch tree portion, which is constructed of a comparatively small number of MOSFETs, and a second switch branch in the second switch tree portion, which is constructed of a comparatively large number of MOSFETs, are controlled `one` and `off` by the same input signal, while a second switch branch in the first switch tree portion, which is constructed of a comparatively large number of MOSFETs, and a first switch branch in the second switch tree portion, which is constructed of a comparatively small number of MOSFETs, are controlled `on` and `off` by the same input signal.