Patents Assigned to Hitachi VLSI Engineering
  • Patent number: 6064593
    Abstract: A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: May 16, 2000
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Patent number: 5297097
    Abstract: Disclosed is a one-chip ULSI which can carry out fixed operations for a wide range of power supply voltages (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which provides a fixed internal voltage for a wide range of power supply voltages, an input/output buffer which can be adapted to several input/out interface levels, a dynamic or volatile RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.
    Type: Grant
    Filed: June 14, 1989
    Date of Patent: March 22, 1994
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering
    Inventors: Jun Etoh, Kiyoo Itoh, Yoshiki Kawajiri, Yoshinobu Nakagome, Eiji Kume, Hitoshi Tanaka
  • Patent number: 5202969
    Abstract: In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
    Type: Grant
    Filed: April 21, 1992
    Date of Patent: April 13, 1993
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering
    Inventors: Katsuyuki Sato, Tadahiko Nishimukai, Kunio Uchiyama, Hirokazu Aoki, Susumu Hatano, Kanji Oishi, Hiroshi Fukuta, Takashi Kikuchi, Yasuhiko Saigou
  • Patent number: 5021998
    Abstract: Disclosed are measurement (observation) pads for judging whether or not a dynamic random access memory (DRAM) adopting a shared sense system is functioning as designed. Concretely, measurement pads are formed by the step of forming a second layer of wiring respectively connected to pairs of complementary data lines which are formed by the step of forming a first layer of wiring, and the signal waveforms of the pairs of complementary data lines are measured using the measurement pads. Further, the measurement pads are provided between wiring layers which become fixed potentials in, at least, the operation of measuring data. In addition, each of the measurement pads is used in common by data lines which are respectively connected to two memory cells located in different memory cell mats.
    Type: Grant
    Filed: April 18, 1989
    Date of Patent: June 4, 1991
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering
    Inventors: Yukihide Suzuki, Masaya Muranaka, Masamichi Ishihara