Abstract: Using a comparatively low supply voltage of, e.g., +5V and a minus gate voltage, the voltage difference between the gate of an MNOS transistor and a P-type well region in which a MNOS transistor is formed is relatively changed to execute the writing and erasing of the MNOS transistor. Thus, the potential of an N-type semiconductor substrate can be fixed to a comparatively low potential, e.g., about +5V, so that a P-channel MOSFET formed on the semiconductor substrate operates with an ordinary signal level. Consequently, an EEPROM having peripheral circuits constructed of CMOS circuits can be provided. Accordingly, reduction in the power consumption of the EEPROM can be attained.