Abstract: Provided herein are apparatus and methods for fast charge pump holdover on signal interruption. In certain configurations, a clock generator system includes a phase-locked loop (PLL), a fast detect circuit, and a switch electrically coupled to an input of the PLL's loop filter. The fast detect circuit relatively quickly detects when an input signal to the PLL is lost. The fast detect circuit can quickly detect the loss of phase lock and can place the PLL into a holdover such that the frequency of a clock signal generated by the PLL remains within an acceptable range.

Abstract: An integrated RF switch module including a package customized to include at least one trace. The trace includes one or more of at least one connection pad and at least one landing pad. At least one switching die is connected to the at least one connection pad. At least one device is connected to the at least one landing pad, the at least one device configured to enhance the performance of the switching die.

Abstract: A resistive sensor read-out apparatus is disclosed. In one embodiment, the resistive sensor read-out apparatus comprises an active sensor, a reference element, a bias circuit, a current-to-voltage converter, an analog-to-digital converter and a calibration processor. The bias circuit is coupled to the active sensor and the reference element and configured to calibrate one or more mismatches between the active sensor and the reference element. The current-to-voltage converter is coupled to an output of the bias circuit. The analog-to-digital converter is coupled to an output of the current-to-voltage converter. The calibration processor is coupled to an output of the analog-to-digital converter and configured to estimate an error caused by limited resolution mismatch calibration. The calibration processor is also configured to at least partially control calibration performed at the bias circuit based on the error.

Abstract: A fast turn on compensation system for a synthesized signal source includes a synthesized signal source coupled to a power supply and configured to generate a phase stable radio frequency (RF) output signal. A mute amplifier is coupled to the synthesized signal source and the power supply. A dummy amplifier is coupled to the mute amplifier and the power supply. A mute controller is coupled to the mute amplifier and the dummy amplifier, the mute controller is responsive to an enable signal and configured to enable the dummy amplifier and disable the mute amplifier when no RF output signal is being generated and disable the dummy amplifier and enable the mute amplifier when the RF output signal is being generated such that total power supply current delivered to the synthesized signal source and the dummy amplifier or mute amplifier is approximately constant before, during, and after enabling the mute amplifier to reduce phase disturbance of the RF output signals.

Abstract: An edge launch and fabrication method wherein spaced elongated slots are formed through a circuit board. The slots are plated at least along one side thereof connecting ground planes of the circuit board thus forming spaced edge plated regions. Circuit modules are produced by singulating the circuit board along a cut line offset outwardly from the plated slot sides to form an edge launch outwardly extending from and between the spaced edge plated regions.

Abstract: A wideband bandpass filter includes an RF input terminal, an RF output terminal, a plurality of electrically tunable coupling capacitors coupled in series between the RF input and output terminals, and a plurality of resonating circuits each including an electrically tunable resonator capacitor coupled to one of the coupling capacitors. At least one resistance is coupled in series between at least one of the coupling capacitors for providing enhanced out of band rejection of the filter.

Abstract: An internally, resistively, sensed Darlington amplifier includes a Darlington amplifier, at least an input transistor, an output transistor, a resistive divider, a signal input node, and a signal output node. The Darlington amplifier is responsive to an input signal and configured to generate an output signal. An internal bias setting resistor is coupled between the signal output node, a collector of the output transistor, and the resistive divider. The bias setting resistor is configured to set and regulate the bias current of the Darlington amplifier.

Abstract: A tunable bandpass filter integrated circuit includes a filter core including at least two spaced conductor layers, a plurality of peripherally spaced backside vias extending between the conductor layers defining a resonator cavity, at least one internal backside via, and a tunable impedance connected in series with the internal backside via between the conductor layers for adjusting the resonance of the cavity.

Abstract: A cavity resonator integrated on a monolithic microwave integrated circuit (MMIC) is provided. The cavity resonator includes a cavity defined by an upper metal surface and a lower metal surface embedded in a low conductivity semiconductor, and a plurality of discrete metal connections coupled between the upper and lower metal surfaces, and at least one port for coupling to the cavity electromagnetically.

Abstract: This invention features an absorptive tunable bandstop filter with a wide tuning range including first and second branches of all-pass filter networks, an input power divider for splitting the input signal and passing approximately half of the input signal power through each branch of the all-pass filter networks, and an output power combiner for recombining the signal power from each branch of the all-pass filter networks, at least one of the branches of the all-pass filter networks being electrically tunable to provide an approximately 180° phase difference with similar amplitudes of the split signal power to be recombined at the output power combiner for rejecting but substantially absorbing selected frequencies.

Abstract: An injection locked pulsed oscillator includes a voltage controlled oscillator (VCO) responsive to an injection signal. The injection locked pulsed oscillator includes at least one enable circuit responsive to a first enable signal to enable output pulses from the VCO. The injection locked pulsed oscillator also includes timing circuit responsive to a pulse repetition frequency signal and is configured to provide the injection signal to phase lock the VCO and provide the first enable signal delayed from the injection signal to shape a width of the output pulses from the VCO.

Abstract: A dynamic dithering method is provided for improving linearity in analog-to-digital converters.

Abstract: A voltage controlled oscillator including an RF output terminal and a DC control terminal, an active circuit, and a resonant circuit interconnected with the active circuit and including a plurality of series resonators each having an electrically variable capacitance and fixed inductor; the active circuit includes at least one transistor having an operating current density which is approximately 35% or less of the peak fT operating current density and/or the active circuit includes a multi-transistor bank disposed in at least two separate sections, each pair of sections spaced apart to provide improved thermal uniformity among the transistors without substantially increasing parasitic impedance among them for providing an improved lower phase noise output at said RF output terminal.

Abstract: An analog-to-digital-converter includes an input signal connector, an output signal port, two or more sub-ADCs, and a digital signal processing block. The result from each sub-ADC is used by the digital signal processing block to output data with increased performance.

Abstract: Methods and apparatus are provided for calibrating stages in pipeline analog-to-digital converters (ADCs) having multiple channels.

Abstract: An improved local oscillator (LO) driver circuit for a mixer, the LO driver circuit includes a gain circuit responsive to LO input signals at a predetermined LO frequency range. At least a first pair of a parallel combination of a resistor and a capacitor is coupled to the gain circuit and to LO inputs of the mixer. The resistor configured to increase impedance at low frequencies of the frequency range and the capacitor is configured to reduce the impedance of the first parallel combination at high frequencies of the frequency range to reduce resistive impendence of the resistor. At least a second pair of a parallel combination of a low quality factor inductor and a high quality factor inductor is connected to the first pair. The second pair in serial combination with the first pair is tuned to provide a constant desired load impedance and a constant desired voltage swing at the LO inputs of the mixer over the predetermined LO frequency range.

Abstract: A circuit comprising an input, two or more sampling capacitors, means for connecting each sampling capacitor to said input, means for discharging the sampling capacitors to a given voltage in a reset phase, means to use the voltage across the sampling capacitor for further processing in a hold phase, operating the two sampling capacitors in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in hold phase.

Abstract: A low pass filter includes an RF input terminal, an RF output terminal, a plurality of inductors coupled in series between the RF input and output terminals, at least one electrically tunable capacitor coupled between ground and a node of one of the inductors. At least one of the inductors includes a winding, and a resistance and a capacitance coupled in series across a portion of the winding to enhance the out of band rejection of the low pass filter.

Abstract: A microstrip combline bandpass filter includes an input port, an output port, and a plurality of resonators each including a microstrip line having a first end and a second end. One of the plurality of resonators is connected to the input port, and another of the plurality of resonators is connected to the output port. The filter also includes a plurality of pairs of series coupled varactors. The first end of each microstrip line is coupled to one of the pairs of varactors, and the second end of each microstrip line is coupled to ground.

Abstract: An internally, resistively, sensed Darlington amplifier includes a Darlington amplifier, at least an input transistor, an output transistor, a resistive divider, a signal input node, and a signal output node. The Darlington amplifier is responsive to an input signal and configured to generate an output signal. An internal bias setting resistor is coupled between the signal output node, a collector of the output transistor, and the resistive divider. The bias setting resistor is configured to set and regulate the bias current of the Darlington amplifier.