Abstract: The track-and-hold circuit includes a switching circuit and a plurality of storage devices. The switching circuit responsive to an input signal applies a representation of the input signal to the storage devices in a track mode and blocks a signal path between the input signal and the storage device in a hold mode such that a transition from the track mode to a hold mode causes the storage devices to store a time sample of the input signal. An acquisition glitch suppression circuit includes a replica amplifier coupled to the switching circuit that senses a differential voltage across the storage devices. A switched clamping circuit clamps inputs of the switching circuit to the sensed differential voltage in the hold mode such that the initial condition of switching transistors of the switching circuit are approximately identical prior to a hold-to-track transition to mitigate differential acquisition glitch.

Abstract: A distributed amplifier includes an input transmission circuit, an output transmission circuit, at least one cascode amplifier coupled between said input and output transmission circuits. Each cascode amplifier includes a first common-gate configured transistor coupled to the output transmission circuit, a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor, and a second common-gate configured transistor coupled between the first common-gate configured transistor and common-source configured transistor.

Abstract: A distributed amplifier with improved stabilization includes an input transmission circuit, an output transmission circuit, at least one cascode amplifier coupled between said input and output transmission circuits. Each cascode amplifier includes a common-gate configured transistor coupled to the output transmission circuit, and a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor. The distributed amplifier also includes a non-parasitic resistance and capacitance coupled in series between a drain and a gate of at least one of the common-gate configured transistors for increasing the amplifier stability.

Abstract: Disclosed herein are power detectors and methods for detecting the average power level of an RF input signal and the voltage envelope of the RF input signal. Also disclosed herein are linear envelope detectors and methods for detecting the voltage envelope of an RF input signal.

Abstract: Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock.

Abstract: Disclosed herein are power detectors and methods for detecting the average power level of an RF input signal and the voltage envelope of the RF input signal. Also disclosed herein are linear envelope detectors and methods for detecting the voltage envelope of an RF input signal.

Abstract: Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready.

Abstract: A distributed amplifier with improved stabilization includes an input transmission circuit, an output transmission circuit, at least one cascade amplifier coupled between said input and output transmission circuits. Each cascade amplifier includes a common-gate configured transistor coupled to the output transmission circuit, and a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor. The distributed amplifier also includes a non-parasitic resistance and capacitance coupled in series between a drain and a gate of at least one of the common-gate configured transistors for increasing the amplifier stability.