Abstract: A continuous-time delta sigma converter includes a loop filter having a plurality of serially coupled integrators including a first integrator responsive to an input of the Delta Sigma converter and a last integrator responsive to a first feedback loop and providing an integrated output signal, and a voltage controlled oscillator (VCO) based quantizer responsive to the loop filter for integrating the integrated output signal and providing a digital output signal. The first feedback loop includes a first time delay circuit responsive to the output of the quantizer and at least one switched capacitor digital to analog converter (DAC) responsive to the first time delay circuit. The first feedback loop is configured to differentiate the digital output signal twice and provide the last integrator of the loop filter with a double differentiated analog signal to reduce excess loop delay.

Abstract: A dynamic dithering method is provided for improving linearity in analog-to-digital converters.

Abstract: A calibration control circuit is provided for calibrating a stage in a pipeline analog-to-digital converter (ADC). The stage includes an analog-to-digital subconverter (ADSC) and a multiplying digital-to-analog converter (MDAC). The calibration control circuit includes circuitry coupled to comparators in the ADSC to force the comparators to output a predetermined digital output signal set by a calibration control signal when the ADC is in a calibration mode to thereby control reference switches in an analog multiplexer (AMUX) to selectively apply reference voltages to capacitors in the MDAC to obtain a predetermined stage residue signal.

Abstract: A continuous time ?? analog-to-digital converter with mitigation bit shifting multiplex array including a loop filter, a VCO responsive to analog signal configured to adjust the output frequency based on the magnitude of the analog signal and produce a digital output, a multi-stage phase quantizer responsive to the digital output configured to determine the phase of the VCO by comparing the phase of the VCO for a particular sample to a reference phase at said particular sample and generate a quantized phase difference value, and a multiplexer array coupled to the multi-stage phase quantizer configured to shift selected misaligned bits of the quantized phase difference value by a predetermined amount of bits to mitigate bit shifting of the multi-stage phase quantizer.

Abstract: Methods and apparatus are provided for calibrating stages in pipeline analog-to-digital converters (ADCs) having multiple channels.

Abstract: A variable gain amplifier includes a plurality of amplification elements arranged to generate amplified representations of an RF input signal at a plurality of nodes. A plurality of controllable response elements each have an input coupled to a different one of the nodes to receive a different one of the amplified representations of the RF input signal. A scale factor generator is coupled to each of the controllable response elements. The scale factor generator receives a gain control signal and generates scale factor signals for varying the response of each of the controllable response elements such that as the scale factor generator sweeps through a full range of the gain control signal, the response of each of the controllable response elements is, in succession, increased smoothly to a peak and thereafter decreased smoothly to a lower level to produce a scaled output.

Abstract: A variable gain amplifier (VGA) disclosed herein includes: an input voltage connector; a number of voltage to current converter circuits generating signal currents; a gain adjustment connector adapted to a current steering mechanism; current mirrors connected to each of the voltage to current converters copying the signal currents; and a steering mechanism adapted to steer the copied currents to a load resistor or to another appropriate location based on the signal present at the gain adjustment connector.

Abstract: An analog-to-digital converter (ADC) apparatus comprising an input signal connector, an output signal port, two or more sub-ADCs, a digital signal processing (DSP) block, wherein the result from each sub-ADC is used by the DSP block to output data with increased performance and perform calibration of each sub-ADC independently while the other sub-ADCs and the DSP block operate and output data normally.

Abstract: A variable gain amplifier (VGA) disclosed herein includes an input current connector, an output current connector, a gain adjustment connector, scaled current mirrors copying the input current, means for steering the copied currents either to the current output or to another appropriate location based on the signal present at the gain adjustment connector.

Abstract: Methods and apparatus are provided for calibrating a pipeline analog-to-digital converter including one or more serially connected analog-to-digital pipeline stages and a back-end analog-to-digital converter.

Abstract: An embodiment of an LNA includes a voltage input, a voltage output, an input transistor connected as a source follower with a current source at the drain and source nodes of the input transistor, an input resistor connected between the source follower source node and signal ground, a gain boosting transistor with the gate connected to the input transistor drain node, wherein the source node is connected to ground and the drain node is connected through a load resistor to the input transistor source node. Such an LNA provides substantial improvement in power efficiency by adapting an output stage of the LNA to reuse the supply current of the input transistors to the LNA through a load resistor.