Abstract: A device for use when exchanging data between two processor units comprises a first processor unit, which is arranged to selectively operate in one of a synchronous mode and an asynchronous mode when exchanging data with a second processor unit through a data memory area in a common memory. Preferably, the access to the data memory area is controlled by a state machine in the first processor unit. The state machine has a first state in which the data memory area is free, a second and a third state in which the data memory area is reserved for the first processor unit and the second processor unit, respectively, and a fourth and a fifth state, in which the data memory area is accessed by the first processor unit and the second processor unit, respectively. The device is advantageously used in a fieldbus system.