Abstract: The present invention relates to a circuit arrangement which comprises at least one 3-level pulse width modulation inverter with a snubber circuit. The snubber circuit is formed by at least one coil (L), two capacitors (Cu, Co) and a series connection comprising four diodes (Dh1-Dh4) poled in the same direction, whereof the two outer diodes (Dh1, Dh4) are in each case directly connected to the input terminals (1, 3) for the positive and the negative pole of the input voltage. The electrical connection between the two inner diodes (Dh2, Dh3) is connected on the one hand via the coil (L) to the input terminal (2) for the center tap of the input voltage and on the other hand to the middle bridge branch of the pulse width modulation inverter. In one embodiment, the two capacitors (Cu, Co) are in each case connected with one terminal to the electrical connection between one of the inner diodes (Dh2, Dh3) and one of the outer diodes (Dh1, Dh4) and with the other terminal directly to the output terminal (4).